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MPC8347ECVRADDB 数据表(PDF) 78 Page - Freescale Semiconductor, Inc |
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MPC8347ECVRADDB 数据表(HTML) 78 Page - Freescale Semiconductor, Inc |
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78 / 99 page  MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 78 Freescale Semiconductor Clocking Addressed by This Document,” for part ordering details and contact your Freescale Sales Representative or authorized distributor for more information. Table 59 provides the operating frequencies for the MPC8347EA PBGA under recommended operating conditions. Table 58. Operating Frequencies for TBGA Characteristic1 1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal operating frequency of the Security core and USB modules does not exceed the respective values listed in this table. 400 MHz 533 MHz 667 MHz Unit e300 core frequency (core_clk) 266–400 266–533 266–667 MHz Coherent system bus frequency (csb_clk) 100–266 100–333 100–333 MHz DDR1 memory bus frequency (MCK)2 2 The DDR data rate is 2x the DDR memory bus frequency. 100–133 100–133 100–166.67 MHz DDR2 memory bus frequency (MCK)3 3 The DDR data rate is 2x the DDR memory bus frequency. 100–133 100–200 100–200 MHz Local bus frequency (LCLKn)4 4 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the csb_clk frequency (depending on RCWL[LBIUCM]). 16.67–133 16.67–133 16.67–133 MHz PCI input frequency (CLKIN or PCI_CLK) 25–66 25–66 25–66 MHz Security core maximum internal operating frequency 133 133 166 MHz USB_DR, USB_MPH maximum internal operating frequency 133 133 166 MHz Table 59. Operating Frequencies for PBGA Parameter1 1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal operating frequency of the Security core and USB modules does not exceed the respective values listed in this table. 266 MHz 333 MHz 400 MHz Unit e300 core frequency (core_clk) 200–266 200–333 200–400 MHz Coherent system bus frequency (csb_clk) 100–266 MHz DDR1 memory bus frequency (MCK)2 2 The DDR data rate is 2× the DDR memory bus frequency. 100–133 MHz DDR2 memory bus frequency (MCK)3 100–133 MHz Local bus frequency (LCLKn)4 16.67–133 MHz PCI input frequency (CLKIN or PCI_CLK) 25–66 MHz Security core maximum internal operating frequency 133 MHz USB_DR, USB_MPH maximum internal operating frequency 133 MHz |
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