AT45DB080

8

Reset Timing (Inactive Clock Polarity Low Shown)

Command Sequence for Read/Write Operations (Except Status Register Read)

Notes:

1.

“r” designates bits reserved for larger densities.

2.

It is recommended that “r” be a logical “0” for densities of 8M bit or smaller.

3.

For densities larger than 8M bit, the “r” bits become the most significant Page Address bit for the appropriate density.

CS

SCK

RESET

SO

HIGH IMPEDANCE

HIGH IMPEDANCE

SI

tRST

tREC

tCSS

I/O7-I/O0

(INPUT)

CMD

ADDR

ADDR

ADDR

MSB

Reserved for

larger densities

Page Address

(PA11-PA0)

Byte/Buffer Address

(BA8-BA0/BFA8-BFA0)

LSB

r r r X X X X X

X X X X X X X X

X X X X X X X X