AT45DB080

5

can be loaded into buffer 2 (or vice versa). See application

note AN-4 (“Using Atmel’s Serial DataFlash”) for more

details.

HARDWARE PAGE WRITE PROTECT: If the WP pin is

held low, the first 256 pages of the main memory cannot be

reprogrammed. The only way to reprogram the first 256

pages is to first drive the protect pin high and then use the

program commands previously mentioned. The WP pin is

internally pulled high; therefore, in low pin count applica-

tions, connection of the WP pin is not necessary if this pin

and feature will not be utilized. However, it is recom-

mended that the WP pin be driven high externally when-

ever possible.

RESET: A low state on the reset pin (RESET) will terminate

the operation in progress and reset the internal state

machine to an idle state. The device will remain in the reset

condition as long as a low level is present on the RESET

pin. Normal operation can resume once the RESET pin is

brought back to a high level.

The device incorporates an internal power-on reset circuit,

so there are no restrictions on the RESET pin during

power-on sequences. The RESET pin is also internally

pulled high; therefore, in low pin count applications, con-

nection of the RESET pin is not necessary if this pin and

feature will not be utilized. However, it is recommended

that the RESET pin be driven high externally whenever

possible.

READY/BUSY: This open drain output pin will be driven

low when the device is busy in an internally self-timed oper-

ation. This pin, which is normally in a high state (through an

external pull-up resistor), will be pulled low during program-

ming operations, compare operations, and during page-to-

buffer transfers.

The busy status indicates that the Flash memory array and

one of the buffers cannot be accessed; read and write

operations to the other buffer can still be performed.

Power On/Reset State

When power is first applied to the device, or when recover-

ing from a reset condition, the device will default to the

“Inactive Clock Polarity High” mode. In addition, the output

pins (I/O

high to low transition on the CS pin will be required to start

a valid instruction. The Clock Polarity mode will be auto-

matically selected on every falling edge of CS by sampling

the inactive clock state.

Note:

ational mode is started.

Absolute Maximum Ratings*

Temperature Under Bias.......................-55

°C to +125°C

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature............................-65

°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground......................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground................... -0.6V to V

DC and AC Operating Range

AT45DB081

Operating Temperature (Case)

Com.

0

°C to 70°C

Ind.

-40

°C to 85°C

V

(1)

2.7V to 3.6V