I2CSTAT datasheet(203/210 Pages) MICROCHIP

203 / 210 page

DS70139G-page 203

dsPIC30F2011/2012/3012/3013

Interrupt Controller

Interrupt Priority .................................................................. 66

Traps........................................................................... 67

Interrupt Sequence ............................................................. 69

Interrupt Stack Frame ................................................. 69

Interrupts ............................................................................. 65

Load Conditions ................................................................ 160

Low Voltage Detect (LVD) ................................................ 133

Low-Voltage Detect Characteristics .................................. 157

LVDL Characteristics ........................................................ 157

Memory Organization.......................................................... 29

Core Register Map...................................................... 39

Microchip Internet Web Site .............................................. 205

Modulo Addressing ............................................................. 44

Applicability ................................................................. 46

Incrementing Buffer Operation Example..................... 45

Start and End Address................................................ 45

W Address Register Selection .................................... 45

MPLAB ASM30 Assembler, Linker, Librarian ................... 146

MPLAB Integrated Development Environment Software .. 145

MPLAB PM3 Device Programmer .................................... 148

MPLAB REAL ICE In-Circuit Emulator System................. 147

MPLINK Object Linker/MPLIB Object Librarian ................ 146

NVM

OC/PWM Module Timing Characteristics.......................... 171

Operating Current (IDD)..................................................... 152

Operating Frequency vs Voltage

dsPIC30FXXXX-20 (Extended)................................. 150

Oscillator

Configurations........................................................... 126

Fail-Safe Clock Monitor .................................... 128

Fast RC (FRC) .................................................. 127

Initial Clock Source Selection ........................... 126

Low-Power RC (LPRC)..................................... 127

LP Oscillator Control ......................................... 127

Phase Locked Loop (PLL) ................................ 127

Start-up Timer (OST) ........................................ 126

Operating Modes (Table) .......................................... 124

System Overview ...................................................... 123

Oscillator Selection ........................................................... 123

Oscillator Start-up Timer

Timing Characteristics .............................................. 165

Timing Requirements................................................ 165

Output Compare Interrupts ................................................. 90

Output Compare Module..................................................... 87

Timing Characteristics .............................................. 170

Timing Requirements................................................ 170

Output Compare Operation During CPU Idle Mode............ 90

Output Compare Sleep Mode Operation ............................ 90

Packaging Information ...................................................... 187

Marking ............................................................. 187, 188

Peripheral Module Disable (PMD) Registers .................... 135

Pinout Descriptions ............................................................. 16

PLL Clock Timing Specifications ...................................... 162

POR. See Power-on Reset.

Port Write/Read Example ................................................... 60

PORTB

PORTC

PORTD

PORTF

Power Saving Modes........................................................ 133

Idle............................................................................ 134

Sleep ........................................................................ 133

Sleep and Idle........................................................... 123

Power-Down Current (IPD)................................................ 154

Power-up Timer

Timing Characteristics .............................................. 165

Timing Requirements ............................................... 165

Program Address Space..................................................... 29

Construction ............................................................... 31

Data Access from Program Memory Using

Program Space Visibility..................................... 33

Data Access From Program Memory Using

Table Instructions ............................................... 32

Data Access from, Address Generation ..................... 31

Data Space Window into Operation ........................... 34

Data Table Access (LS Word) .................................... 32

Data Table Access (MS Byte) .................................... 33

Memory Maps............................................................. 30

Table Instructions

TBLRDH ............................................................. 32

TBLRDL.............................................................. 32

TBLWTH............................................................. 32

TBLWTL ............................................................. 32

Program and EEPROM Characteristics............................ 159

Program Counter ................................................................ 20

Programmable .................................................................. 123

Programmer’s Model .......................................................... 20

Diagram ...................................................................... 21

Programming Operations.................................................... 51

Algorithm for Program Flash....................................... 51

Erasing a Row of Program Memory ........................... 51

Initiating the Programming Sequence ........................ 52

Loading Write Latches................................................ 52

Protection Against Accidental Writes to OSCCON ........... 128

Reader Response............................................................. 206

Reset ........................................................................ 123, 129

BOR, Programmable ................................................ 131

Brown-out Reset (BOR)............................................ 123

Oscillator Start-up Timer (OST) ................................ 123

POR

Operating without FSCM and PWRT................ 131

With Long Crystal Start-up Time ...................... 131

POR (Power-on Reset)............................................. 129

Power-on Reset (POR)............................................. 123

Power-up Timer (PWRT) .......................................... 123

Reset Sequence ................................................................. 67

Reset Sources ............................................................ 67

Reset Sources

Brown-out Reset (BOR).............................................. 67

Illegal Instruction Trap ................................................ 67

I2CSTAT 数据表(PDF) 203 Page - Microchip Technology

I2CSTAT 数据表(HTML) 203 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载