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PCM3003 数据表(PDF) 2 Page - Burr-Brown (TI) |
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PCM3003 数据表(HTML) 2 Page - Burr-Brown (TI) |
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2 / 23 page  ® PCM3002/3003 2 SPECIFICATIONS All specifications at +25 °C, V DD = VCC = 3.0V, fS = 44.1kHz, SYSCLK = 384fS, and 16-bit data, unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. NOTES: (1) Pins 7, 8, 17 and 18: RST, ML, MD, MC for the PCM3002; PDAD, PDDA, DEM1, DEM0 for PCM3003 (Schmitt-Trigger input with 100k Ω typical internal pull-down resistor). (2) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt Trigger input). (3) Pin16: 20BIT for PCM3003 (Schmitt-Trigger input, 100k Ω typical internal pull-down resistor). (4) Pin 12: DOUT. (5) Pin 16: ZFLG (open drain output). (6) High Pass Filter for Offset Cancel. (7) Refer to Application Bulletin AB-148 for information relating to operation at lower sampling frequencies. (8) fIN = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (9) fOUT = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (10) Applies for voltages between 2.4V to 2.7V for 0 °C to +70°C and 256f S /512fS operation (384fS not available). (11) SYSCLK, BCKIN, and LRCIN are stopped. PCM3002E/3003E PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUT/OUTPUT Input Logic Input Logic Level: VIH(1, 2, 3) 0.7 x VDD VDC VIL(1, 2, 3) 0.3 x VDD VDC Input Logic Current: IIN(2) ±1 µA Input Logic Current: IIN(1) 100 µA Output Logic Output Logic Level: VOH(5) IOUT = –1mA VDD –0.3 VDC VOL(5) IOUT = +1mA 0.3 VDC Output Logic Level: VOL(4) IOUT = +1mA 0.3 VDC CLOCK FREQUENCY Sampling Frequency (fS) 32(7) 44.1 48 kHz System Clock Frequency 256fS 8.1920 11.2896 12.2880 MHz 384fS 12.2880 16.9344 18.4320 MHz 512fS 16.3840 22.5792 24.5760 MHz ADC CHARACTERISTICS RESOLUTION 20 Bits DC ACCURACY Gain Mismatch Channel-to-Channel ±1.0 ±3.0 % of FSR Gain Error ±2.0 ±5.0 % of FSR Gain Drift ±20 ppm of FSR/ °C Bipolar Zero Error High-Pass Filter Disabled(6) ±1.7 % of FSR Bipolar Zero Drift High-Pass Filter Disabled(6) ±20 ppm of FSR/ °C DYNAMIC PERFORMANCE(8) THD+N: VIN = –0.5dB –86 –80 dB VIN = –60dB –28 dB Dynamic Range A-Weighted 86 90 dB Signal-to-Noise Ratio A-Weighted 86 90 dB Channel Separation 84 88 dB DIGITAL FILTER PERFORMANCE Passband 0.454fS Hz Stopband 0.583fS Hz Passband Ripple ±0.05 dB Stopband Attenuation –65 dB Delay Time 17.4/fS sec HPF Frequency Response –3dB 0.019fS mHz ANALOG INPUT Voltage Range 0.60 VCC Vp-p Center Voltage 0.50 VCC V Input Impedance 30 k Ω Anti-Aliasing Filter Frequency Response –3dB 150 kHz |
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