®

PCM3002/3003

16

LRCIN is synchronized with 5 or less bit clocks to the system

clock, operation will be normal. Figure 9 illustrates the effects

on the output when synchronization is lost. Before the outputs

defined and some noise may occur. During the transitions

between normal data and undefined states, the output has

discontinuities, which will cause output noise.

ZERO FLAG OUTPUT: PCM3002 ONLY

Pin 16 is an open-drain output, used as the infinite zero

detection flag on the PCM3002 only. When input data is

continuously zero for 65,536 BCKIN cycles, ZFLG is LOW,

otherwise, ZFLG is in a high-impedance state.

Synchronous

Asynchronous

Synchronization

Lost

Resynchronization

within

1/f

S

Synchronous

Normal

Normal

t

t

Undefined Data

V

COM

(= 1/2 x V

Undefined Data

State of

Synchronization

DAC V

OUT

Normal

Zero

ADC DOUT

NOTES: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR

with 200ms time constant) appears initially.

Reset

Power Down

GND

V

COM

(0.5V

Ready/Operation

Internal Reset

or Power Down

ADC DOUT

DAC V

OUT

Zero

Zero

t

t

Reset Removal or Power Down OFF

NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR

with 200ms time constant) appears initially.

SYNCHRONIZATION WITH THE DIGITAL

AUDIO SYSTEM

The PCM3002/3003 operates with LRCIN synchronized to

the system clock. PCM3002/3003 does not require any spe-

cific phase relationship between LRCIN and the system

clock, but there must be synchronization. If the synchroniza-

tion between the system clock and LRCIN changes more than

6 bit clocks (BCKIN) during one sample (LRCIN) period

because of phase jitter on LRCIN, internal operation of the

the digital output codes will be set to bipolar zero until re-

FIGURE 8. DAC Output and ADC Output for Reset and Power Down.

FIGURE 9. DAC Output and ADC Output for Loss of Synchronization.