PCM3003 datasheet(18/23 Pages) BURR-BROWN

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PCM3002/3003

B15

B14

B13

B12

B11

B10

res

LDL

AL7

AL6

AL5

AL4

AL3

AL2

AL1

AL0

res

LDR

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

res

PDAD

BYPS

PDDA

ATC

IZD

OUT

DEM1

DEM0

MUT

res

LOP

res

FMT1

FMT0

LRP

res

MAPPING OF PROGRAM REGISTERS

SOFTWARE CONTROL (PCM3002)

PCM3002’s special functions are controlled using four pro-

gram registers which are 16 bits long. There are four distinct

registers, with bits 9 and 10 determining which register is in

use. Table III describes the functions of the four registers.

BIT

NAME

DESCRIPTION

A (1:0)

res

Reserved, should be set to “0”

LDL

DAC Attenuation Data Load Control for Lch

AL (7:0)

Attenuation Data for Lch

A (1:0)

res

Reserved, should be set to “0”

LDR

DAC Attenuation Data Load Control for Rch

AR (7:0)

DAC Attenuation for Rch

A (1:0)

res

Reserved, should be set to “0”

PDAD

ADC Power-Down Control

PDDA

DAC Power-Down Control

BYPS

ADC High-Pass Filter Operation Control

ATC

DAC Attenuation Data Mode Control

IZD

DAC Infinite Zero Detection Circuit Control

OUT

DAC Output Enable Control

DEM (1:0)

DAC De-emphasis Control

MUT

Lch and Rch Soft Mute Control

A (1:0)

res

Reserved, should be set to “0”

LOP

ADC/DAC Analog Loop-Back Control

FMT (1:0)

ADC/DAC Audio Data Format Selection

LRP

ADC/DAC Polarity of LR-clock Selection

TABLE III. Functions of the Registers.

PROGRAM REGISTER 0

A (1:0):

Bit 10, 9

These bits define the address for REGISTER 0:

res:

Bit 11 : 15

Reserved

These bits are reserved and should be set to “0”.

LDL:

Bit 8

DAC Attenuation Data Load Control for

Left Channel

This bit is used to simultaneously set analog

outputs of the left and right channels. The output

level is controlled by AL (7:0) attenuation data

when this bit is set to “1”. When set to “0”, the

new attenuation data will be ignored, and the

output level will remain at the previous attenua-

tion level. The LDR bit in REGISTER 1 has the

equivalent function as LDL. When either LDL or

LDR is set to “1”, the output level of the left and

right channels are simultaneously controlled.

AL (7:0): Bit 7:0

DAC Attenuation Data for Left Channel

AL7 and AL0 are MSB and LSB, respectively.

The attenuation level (ATT) is given by:

ATT = 20 x log10 (ATT data/255) (dB)

AL (7:0)

ATTENUATION LEVEL

00h

–

∞dB (Mute)

01h

–48.16dB

FEh

–0.07dB

FFh

0dB (default)

PROGRAM REGISTER 1

A (1:0):

These bits define the address for REGISTER 1:

res:

Bit 15:11

Reserved

These bits are reserved and should be set to “0”

LDR:

Bit 8

DAC Attenuation Data Load Control for

Right Channel

This bit is used to simultaneously set analog

outputs of the left and right channels. The output

level is controlled by AL (7:0) attenuation data

when this bit is set to “1”. When set to “0”, the

new attenuation data will be ignored, and the

output level will remain at the previous attenua-

tion level. The LDL bit in REGISTER 0 has the

equivalent function as LDR. When either LDL or

LDR is set to “1”, the output level of the left and

right channels are simultaneously controlled.

AR (7:0): Bit 7:0

DAC Attenuation Data for Left

Channel

AR7 and AR0 are MSB and LSB respectively.

See REGISTER 0 for the attenuation formula.

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