PCM3003 datasheet(21/23 Pages) BURR-BROWN

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PCM3002/3003

PCM3003 DATA FORMAT CONTROL

PCM3003 has hardware functional control using PDAD (pin

7) and PDDA (pin 8) for Power-Down Control; DEM0 (pin

18) and DEM1 (pin 17) for de-emphasis; and 20BIT (pin 16)

for 16-/20-bit format selection.

Power-Down Control (Pin 7 and Pin 8)

Both the ADC’s and DAC’s Power-Down Control pins

place the ADC or DAC section in the lowest power con-

sumption mode. The ADC/DAC operation is stopped by

cutting the supply current to the ADC/DAC section. DOUT

is fixed to zero during ADC Power-Down Mode enable and

VOUT is fixed to GND during DAC Power-Down Mode

enable. Figure 8 illustrates the ADC and DAC output re-

sponse for Power-Down ON/OFF.

PDAD

PDDA

POWER DOWN

Low

Reset (ADC/DAC Power-Down Enable)

Low

High

ADC Power-Down/DAC Operates

High

Low

ADC Operates/DAC Power-Down

High

ADC and DAC Normal Operation

De-Emphasis Control (Pin 17 and Pin 18)

DEM0 (pin 18) and DEM1 (pin 17) are used as de-emphasis

control pins.

DEM1

DEM0

DE-EMPHASIS

Low

De-Emphasis Enabled for 44.1kHz

Low

High

De-Emphasis Disabled

High

Low

De-Emphasis Enabled for 48kHz

High

De-Emphasis Enabled for 32kHz

20BIT Audio Data Selection (Pin 16)

20BIT

FORMAT

Low

ADC: 16-bit MSB-first, Left-justified

DAC: 16-bit MSB-first, Right-justified

High

ADC: 20-bit MSB-first, Left-justified

DAC: 20-bit MSB-first, Right-justified

APPLICATION AND LAYOUT

CONSIDERATIONS

POWER SUPPLY BYPASSING

The digital and analog power supply lines to PCM3002/

3003 should be bypassed to the corresponding ground pins

with both 0.1

µF ceramic and 10µF tantalum capacitors as

close to the device pins as possible. Although PCM3002/

3003 has three power supply lines to optimize dynamic

performance, the use of one common power supply is

generally recommended to avoid unexpected latch-up or pop

noise due to power supply sequencing problems. If separate

power supplies are used, back-to-back diodes are recom-

mended to avoid latch-up problems.

GROUNDING

In order to optimize the dynamic performance of PCM3002/

3003, the analog and digital grounds are not connected

internally. The PCM3002/3003 performance is optimized

with a single ground plane for all returns. It is recommended

to tie all PCM3002/3003 ground pins with low impedance

connections to the analog ground plane. PCM3002/3003

should reside entirely over this plane to avoid coupling high

frequency digital switching noise into the analog ground

plane.

VOLTAGE INPUT PINS

A tantalum or aluminum electrolytic capacitor, between 1

µF

and 10

µF, is recommended as an AC-coupling capacitor at

the inputs. Combined with the 30k

Ω characteristic input

impedance, a 1.0

µF coupling capacitor will establish a 5.3Hz

cut-off frequency for blocking DC. The input voltage range

can be increased by adding a series resistor on the analog

input line. This series resistor, when combined with the 30k

Ω

input impedance, creates a voltage divider and enables larger

input ranges.

VREF INPUTS

A 4.7

µF to 10µF tantalum capacitor is recommended be-

tween VREFL, VREFR, and AGND to ensure low source

impedance for the ADC’s references. These capacitors should

be located as close as possible to the reference pins to reduce

dynamic errors on the ADC reference.

VCOM INPUTS

A 4.7

µF to 10µF tantalum capacitor is recommended be-

tween VCOM and AGND to ensure low source impedance of

the ADC and DAC common voltage. This capacitor should

be located as close as possible to the VCOM pin to reduce

dynamic errors on the DC common mode voltage.

SYSTEM CLOCK

The quality of the system clock can influence dynamic

performance of both the ADC and DAC in the PCM3002/

3003. The duty cycle and jitter at the system clock input pin

must be carefully managed. When power is supplied to the

part, the system clock, bit clock (BCKIN) and a word clock

(LCRIN) should also be supplied simultaneously. Failure to

supply the audio clocks will result in a power dissipation

increase of up to three times normal dissipation and may

degrade long term reliability if the maximum power dissipa-

tion limit is exceeded.

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