SCF5250 datasheet(36/56 Pages) FREESCALE

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SCF5250 Data Sheet: Technical Data, Rev. 1.3

Freescale Semiconductor

Figure 14 provides the SCLK input/output, SDATA input timing diagram and Table 33 provides the timing

parameters.

Figure 14. SCLK Input/Output, SDATA Input Timing Diagram

Pin-Out and Package Information

Visit the URL [http://www.freescale.com/coldfire] and choose the documentation library to obtain

information on the mechanical characteristics of the SCF5250 integrated microprocessor. Thermal

characteristics are not available at this time.

The SCF5250 is available in a 144 pin QFP and a 196 pin MAPBGA package. Use Table 34 to find the

information desired.

5.1

144 QFP Pin Assignments

The SCF5250 can be assembled in 144-pin QFP package. Table 35 provides the pin assignments for the

package.

Table 33. SCLK Input/Output, SDATA Input Timing Specifications

Num

Characteristic

Min

Max

Units

TSU

SDATAI IN to SCLKn

-5

–

SCLK rise to SDATAI

–

Table 34. Section Quick Reference

For Chip

Package

See

144 pin QFP

Pin assignments

Table 35 on page 37

Package drawings

Figure 15 on page 42

Figure 16 on page 43

Figure 17 on page 44

196 MAPBGA

Pin assignments

Table 36 on page 45

Package drawings

Figure 18 on page 52

Figure 19 on page 53

Ball map

Figure 20 on page 54

SCLK

SDATA1, 3, 4 (INPUT)

TSU

(

INPUT OR OUTPUT)

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