SCF5250 datasheet(9/56 Pages) FREESCALE

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SCF5250 Data Sheet: Technical Data, Rev. 1.3

Freescale Semiconductor

Table 2. SCF5250 Signal Index

Signal Name

Mnemonic

Function

Input/

Output

Reset

State

Address

A[24:1]

A[23]/GPO54

24 address lines, address line 23

multiplexed with GPO54 and address 24

is multiplexed with A20 (SDRAM access

only).

Out

Read-write control

R/W

Bus write enable - indicates if read or

write cycle in progress

Out

Output enable

Output enable for asynchronous

memories connected to chip selects

Out

negated

Data

D[31:16]

Data bus used to transfer word data

In/Out

Hi-Z

Synchronous row address

strobe

SDRAS/GPIO59

Row address strobe for external SDRAM.

Out

negated

Synchronous column

address strobe

SDCAS/GPIO39

Column address strobe for external

SDRAM

Out

negated

SDRAM write enable

SDWE/GPIO38

Write enable for external SDRAM

Out

negated

SDRAM upper byte

enable

SDUDQM/GPO53

Indicates during write cycle if high byte is

written

Out

–

SDRAM lower byte enable SDLDQM/GPO52

Indicates during write cycle if low byte is

written

Out

–

SDRAM chip selects

SD_CS0/GPIO60

SDRAM chip select

In/Out negated

SDRAM clock enable

BCLKE/GPIO63

SDRAM clock enable

Out

–

System clock

BCLK/GPIO40

SDRAM clock output

In/Out

–

ISA bus read strobe

IDE-DIOR/GPIO31

(CS2)

There is 1 ISA bus read strobe and 1 ISA

bus write strobe. They allow connection

of one independent ISA bus peripherals,

e.g. an IDE slave device.

In/Out

–

ISA bus write strobe

IDE-DIOW/GPIO32

(CS2)

In/Out

–

ISA bus wait signal

IDE-IORDY/GPIO33

ISA bus wait line - available for both

busses

In/Out

–

Chip Selects[2:0]

CS0/CS4

CS1/QSPI_CS3/GPIO28

Enables peripherals at programmed

addresses.

CS[0] provides boot ROM selection

Out

In/Out

negated

Buffer enable 1

BUFENB1/GPIO29

Two programmable buffer enables allow

seamless steering of external buffers to

split data and address bus in sections.

In/Out

–

Buffer enable 2

BUFENB2/GPIO30

In/Out

–

Transfer acknowledge

TA/GPIO12

Transfer Acknowledge signal

In/Out

–

Wake Up

WAKE_UP/GPIO21

Wake-up signal input

–

Serial Clock Line

SCL0/SDATA1_BS1/GPIO41

SCL1/TXD1/GPIO10

Clock signal for Dual I2C module

operation

In/Out

–

Serial Data Line

SDA0/SDATA3/GPIO42

SDA1/RXD1/GPIO44

Serial data port for second I2C module

operation

In/Out

–

Receive Data

SDA1/RXD1/GPIO44

RXD0/GPIO46

Signal is receive serial data input for

DUART

–

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