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SCF5250LPV100 数据表(PDF) 27 Page - Freescale Semiconductor, Inc |
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SCF5250LPV100 数据表(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 56 page ![]() SCF5250 Data Sheet: Technical Data, Rev. 1.3 Freescale Semiconductor 27 Figure 4. Input/Output AC Timing Definition-III Table 21. Input AC Timing Specification Num Characteristic Min Max Units B11,2 1 Inputs (rising): DATA[31:16] 2 AC timing specs assume 40pF load capacitance on BCLK and 50pF load capacitance on output pins. If this value is different, the input and output timing specifications would need to be adjusted to match the clock load. Signal Valid to BCLK Rising (setup) 3 – ns B21 BCLK Rising to signal Invalid (hold) 2 – ns B31 BCLK to Input High Impedance – 5 BCLK cycle Table 22. Output AC Timing Specification Num Characteristic1 Min Max Units B102 BCLK (8mA) Rising to signal Valid – 10 ns B112 BCLK (8mA) Rising to signal Invalid (hold) 3.5 – ns B103 BCLK (4mA) Rising to signal Valid – 11 ns B113 BCLK (4mA) Rising to signal Invalid (hold) 4 – ns B124 BCLK to High Impedance (Three-State) – 14 ns B13 B14 BCLK H1 H2 HIZ OUTPUTS OUTPUTS BCLK B3 B4 INPUTS |
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