SCF5250LPV100 datasheet(12/56 Pages) FREESCALE

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SCF5250 Data Sheet: Technical Data, Rev. 1.3

Freescale Semiconductor

3.1

GPIO

Many pins have an optional GPIO function.

•

General purpose input is always active, regardless of state of pin.

•

General purpose output or primary output is determined by the appropriate setting of the Pin

Multiplex Control Registers, GPIO-FUNCTION, GPIO1-FUNCTION and PIN-CONFIG.

•

At Power-on reset, all pins are set to their primary function.

3.2

SCF5250 Bus Signals

These signals provide the external bus interface to the SCF5250 processor.

3.2.1

Address Bus

•

The address bus provides the address of the byte or most significant byte of the word or longword

being transferred. The address lines also serve as the DRAM address pins, providing multiplexed

row and column address signals.

•

Bits 23 down to 1 and 24 of the address are available. A24 is intended to be used with 256 Mbit

DRAM’s. Signals are named:

— A[23:1]

— A20/24

Processor Status

PST0/GPIO50

PST1/GPIO49

PST2/INTMON2/GPIO48

PST3/INTMON1/GPIO47

Indicates internal processor status.

In/Out

Hi-Z

Processor Clock

PSTCLK/GPIO51

processor clock output

Out

–

Test Clock

TCK

Clock signal for IEEE 1149.1A JTAG.

–

Test Reset/Development

Serial Clock

TRST/DSCLK

Multiplexed signal that is asynchronous

reset for JTAG controller. Clock input for

debug module.

–

Test Mode Select/ Break

Point

TMS/BKPT

Multiplexed signal that is test mode select

in JTAG mode and a hardware

break-point in debug mode.

–

Test Data Input /

Development Serial Input

TDI/DSI

Multiplexed serial input for the JTAG or

background debug module.

–

Test Data

Output/Development

Serial Output

TDO/DSO

Multiplexed serial output for the JTAG or

background debug module.

Out

–

Table 2. SCF5250 Signal Index (continued)

Signal Name

Mnemonic

Function

Input/

Output

Reset

State

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