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SCF5250LPV100 数据表(PDF) 29 Page - Freescale Semiconductor, Inc |
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SCF5250LPV100 数据表(HTML) 29 Page - Freescale Semiconductor, Inc |
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29 / 56 page ![]() SCF5250 Data Sheet: Technical Data, Rev. 1.3 Freescale Semiconductor 29 Figure 6 and Table 24 provide the timing diagram and timing parameters for the Timer module. Figure 6. Timer Module AC Timing Definition Diagram Table 24. Timer Module AC Timing Specification Num Characteristic Min Max Units T1 TIN Cycle time 3T – bus clocks T2 TIN Valid to BCLK (input setup) 6 – ns T3 BCLK to TIN Invalid (input hold) 0 – ns T4 BCLK to TOUT Valid (output valid) – 10 ns T5 BCLK to TOUT Invalid (output hold) tbd – ns T6 TIN Pulse Width 1T – bus clocks T7 TOUT Pulse Width 1T – bus clocks BCLK T6 T2 T3 T1 T7 T4 T5 TIN TIN TOUT |
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