HVLED807PF

Device description

Doc ID 023464 Rev 5

19/36

The triggering block is blanked after MOSFET's turn-off to prevent any negative-going edge

that follows leakage inductance demagnetization from triggering the DMG circuit

The voltage on the pin is both top and bottom limited by a double clamp, as illustrated in the

internal diagram of the DMG block of

Figure 14. The upper clamp is typically located at 3.3

V, while the lower clamp is located at -60 mV. The interface between the pin and the

auxiliary winding will be a resistor divider. Its resistance ratio as well as the individual

resistance values will be properly chosen (see

Section 4.6, 4.7 and 4.11).

Please note that the maximum IDMG sunk/sourced current has to not exceed ±2 mA (AMR)

in all the Vin range conditions. No capacitor is allowed between DMG pin and the auxiliary

transformer.

The switching frequency is top-limited below 166 kHz, as the converter's operating

frequency tends to increase excessively at light load and high input voltage.

A Starter block is also used to start-up the system, that is, to turn on the MOSFET during

converter power-up, when no or a too small signal is available on the DMG pin. The starter

frequency is 2 kHz if COMP pin is below burst mode threshold, i.e. 1 V, while it becomes 8

kHz if this voltage exceed this value.

After the first few cycles initiated by the starter, as the voltage developed across the auxiliary

winding becomes large enough to arm the DMG circuit, MOSFET's turn-on will start to be

locked to transformer demagnetization, hence setting up QR operation. The starter is

activated also when the IC is in Constant Current regulation and the output voltage is not

high enough to allow the DMG triggering.

If the demagnetization completes - hence a negative-going edge appears on the DMG pin -

on again, with some delay to ensure minimum voltage at turn-on. If, instead, the negative-

cycles will be skipped ("valley-skipping mode",

Figure 15) and the switching frequency will

Figure 15.

Drain ringing cycle skipping as the load is progressively reduced

Note:

That when the system operates in valley skipping-mode, uneven switching cycles may be

observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET

is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for

cycle-by-cycle energy balance may fall in between. Thus one or more longer switching

cycles will be compensated by one or more shorter cycles and vice versa. However, this

mechanism is absolutely normal and there is no appreciable effect on the performance of

the converter or on its output voltage.

AM13565v1

(limit condition)

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