and provided that PWRGD is low. It is also required that

the overvoltage condition be present for at least the

PWRGD delay time for the OVP signal to be activated. The

set using the following equation:

Figure 13: OVP response to an input-to-output short circuit by immedi-

ately providing 0% duty cycle, crow-barring the input voltage to

ground.

Figure 14: OVP response to an input-to-output short circuit by pulling

the input voltage to ground.

Figure 15: Circuit to implement a dedicated OVP output using the

CS5166.

Power-Good Circuit

The Power-Good pin (pin 13) is an open-collector signal

consistent with TTL DC specifications. It is externally

pulled -up, and is pulled low (below 0.3V) when the regu-

lator output voltage typically exceeds ± 8.5% of the nomi-

nal output voltage. Maximum output voltage deviation

before Power-Good is pulled low is ± 12%.

Figure 17: Power-Good response to an out of regulation condition.

Trace 1 PWRGD (2V/div)

Trace 2 - PWRGD (2V/div)

2.825V

+5V

+5V

VCORE

CS5166

PWRGD

Q1

2N3906

2N3904

Q2

2N3906

Q3

R1

R2

OVP

10K

20K

10K

5K

10K

15K

56K

Trace 4 = 5V from PC Power Supply (2V/div.)

Trace 1 = Regulator Output Voltage (1V/div.)

Trace 4 = 5V from PC Power Supply (5V/div.)

Trace1 = Regulator Output Voltage (1V/div.)

Trace 2 = Inductor Switching Node (5V/div.)

R2

R1

11

Application Information: continued