CS5166 datasheet(19/22 Pages) CHERRY

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Response Time to Load Decrease

(limited by Inductor value)

Response Time =

Example: VOUT = +2.8V, 14.2A change in Load Current,

L = 1.2µH

Response Time =

= 6.1µs

Input and Output Capacitors

These components must be selected and placed carefully to

yield optimal results. Capacitors should be chosen to pro-

vide acceptable ripple on the input supply lines and regu-

lator output voltage. Key specifications for input capacitors

are their ripple rating, while ESR is important for output

capacitors. For best transient response, a combination of

low value/high frequency and bulk capacitors placed close

to the load will be required.

Thermal Considerations for Power MOSFETs and Diodes

In order to maintain good reliability, the junction tempera-

ture of the semiconductor components should be kept to a

maximum of 150°C or lower. The thermal impedance

(junction to ambient) required to meet this requirement can

be calculated as follows:

Thermal Impedance =

A heatsink may be added to TO-220 components to reduce

their thermal impedance. A number of PC board layout

techniques such as thermal vias and additional copper foil

area can be used to improve the power handling capability

of surface mount components.

EMI Management

As a consequence of large currents being turned on and off

at high frequency, switching regulators generate noise as a

consequence of their normal operation. When designing

for compliance with EMI/EMC regulations, additional

components may be added to reduce noise emissions.

These components are not required for regulator operation

and experimental results may allow them to be eliminated.

The input filter inductor may not be required because bulk

filter and bypass capacitors, as well as other loads located

on the board will tend to reduce regulator di/dt effects on

the circuit board and input power supply. Placement of the

power component to minimize routing distance will also

help to reduce emissions.

Figure 27: Filter components.

Figure 28: Input Filter.

Layout Guidelines

When laying out the CPU buck regulator on a printed cir-

cuit board, the following checklist should be used to

ensure proper operation of the CS5166.

1) Rapid changes in voltage across parasitic capacitors and

abrupt changes in current in parasitic inductors are major

concerns for a good layout.

2) Keep high currents out of sensitive ground connections.

Avoid connecting the IC Gnd (LGnd) between the source

of the lower FET and the input capacitor Gnd.

3) Avoid ground loops as they pick up noise. Use star or

single point grounding.

4) For high power buck regulators on double-sided PCBs a

single large ground plane (usually the bottom) is recom-

mended.

5) Even though double-sided PCBs are usually sufficient

for a good layout, four-layer PCBs are the optimum

approach to reducing susceptibility to noise. Use the two

internal layers as the +5V and Gnd planes, the top layer for

the power connections and component vias, and the bot-

tom layer for the noise sensitive traces.

6) Keep the inductor switching node small by placing the

output inductor, switching and synchronous FETs close

together.

7) The FET gate traces to the IC must be as short, straight,

and wide as possible. Ideally, the IC has to be placed right

next to the FETs.

8) Use fewer, but larger output capacitors, keep the capaci-

tors clustered, and use multiple layer traces with heavy

copper to keep the parasitic resistance low.

9) Place the switching FET as close to the +5V input capaci-

tors as possible.

10) Place the output capacitors as close to the load

as possible.

2µH

1200µF x 3/16V

33Ω

1000pF

2µH

TJ(MAX) - TA

Power

Thermal Management

1.2µH × 14.2A

2.8V

L × Change in IOUT

VOUT

Application Information: continued

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