CS5166 datasheet(17/22 Pages) CHERRY

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Application Information: continued

W =

where:

W = minimum width (in mils) required for proper power

dissipation, and ILOAD Load Current Amps.

The Pentium®II maximum load current is 14.2A.

Therefore:

W =

= 284 mils = 0.7213cm

Droop Resistor Length Calculation

L =

= 1626 mil = 4.13cm

Implementing current sharing using the “Droop

Resistor”

In addition to improving load transient performance, the

CS5166 V2

TM control method allows the droop resistor to

provide the additional capability to easily implement cur-

rent sharing. Figure 23 shows a simplified schematic of

two current sharing synchronous buck regulators.

Each buck regulator’s droop resistor is terminated at the

load. The PWM control signal from each Error Amp is con-

nected together, causing the inner PWM loop to regulate to

a common voltage. Since the voltage at each resistor termi-

nal is the same, this configuration results in equal voltage

being applied across each matched droop resistor. The

result is equal current flowing through each buck regula-

tor. An additional benefit is that synchronization to a com-

mon switching frequency tends to be achieved because

each regulator shares a common PWM ramp signal.

In practice, each buck regulator will regulate to a slightly

different output voltage due to mismatching of the PWM

comparators, slope of the PWM ramp (output voltage rip-

ple), and propagation delays. At light loads, the result can

be very poor current sharing. With zero output current,

some regulators may be sourcing current while others may

be sinking current.

This results in additional power dissipation and lower effi-

ciency than would be obtained by a single regulator. This

is usually not an issue since efficiency is most important

when a supply is fully loaded.

This effect is similar to the difference in efficiency between

synchronous and non-synchronous buck regulators.

Synchronous Buck regulators have lower efficiency at light

loads because inductor current is always continuous, flow-

ing from the load to ground during switch off-time

through the synchronous rectifier. Under full load condi-

tions, the synchronous design is more efficient due to the

lower voltage drop across the synchronous rectifier.

Likewise, the efficiency of droop sharing regulators will be

lower at light loads due to the continuous current flow in

the droop resistors. Efficiency at heavy loads tends to be

higher due to reduced I2R losses.

The output current of each regulator can be calculated

from:

IN = (VOUT(N) - VOUT) / RDROOP(N)

where: VOUT(N) and RDROOP(N) are the output voltage and

droop resistance of a particular regulator and VOUT is the

system output voltage. Output current is the sum of each

regulator’s current:

IOUT = I1 + I2 + … + IN

Current sharing improves with increasing load current.

The increasing voltage drop across the droop resistor due

to increasing load current eventually swamps out the dif-

ferences in regulator output voltages. If a large enough

voltage can be developed across the droop resistors, cur-

rent sharing accuracy will be determined solely by their

matching. To realize the benefits of current sharing, it is

not necessary to obtain perfect matching. Keeping output

currents within +/- 10% is usually acceptable.

For microprocessor applications, the value of the droop

resistor must be selected to optimize adaptive voltage

positioning, current sharing, current limit and efficiency.

Current sharing is realized by simply connecting the

COMP pins of the respective buck regulators, as shown in

Figure 23.

Figure 24 shows operation with no load. In this case, there

is insufficient output voltage ripple across the droop resis-

tors to produce complete synchronization. Duty Cycle is

close to the theoretical 56% (VOUT/VIN) resulting in a

switching frequency of approximately 275kHz.

Figure 25 shows operation with a 30 Amp load.

Synchronization between the two regulators is now

obtained due to increased ripple voltage. Increased losses

cause the V2

TM control loop to increase on-time to compen-

sate. This results in a larger duty cycle and a correspond-

ing decrease in switching frequency to 233kHz.

Figure 24: No load waveforms.

Trace 1 Output voltage ripple

Trace 2 Buck regulator #1 inductor switching node

Trace 3 Buck regulator #2 inductor switching node

0.0030 × 284 × 1.37

717.86

RDROOP × W × t

14.2A

0.05

ILOAD

0.05

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