CS43L41

4

DS473PP1

LIST OF FIGURES

Figure 1.

External Serial Mode Input Timing ................................................................................. 9

Figure 2.

Internal Serial Mode Input Timing .................................................................................. 9

Figure 3.

Internal Serial Clock Generation .................................................................................... 9

Figure 4.

Figure 5.

SPI Control Port Timing ...............................................................................................12

Figure 6.

Typical Connection Diagram ........................................................................................ 13

Figure 7.

SPI Mode Control Port Formatting ............................................................................... 28

Figure 8.

Figure 9.

Base-Rate Stopband Rejection .................................................................................... 29

Figure 10. Base-Rate Transition Band .......................................................................................... 29

Figure 11. Base-Rate Transition Band (Detail) ............................................................................. 29

Figure 12. Base-Rate Passband Ripple ........................................................................................ 29

Figure 13. High-Rate Stopband Rejection ..................................................................................... 29

Figure 14. High-Rate Transition Band ........................................................................................... 29

Figure 15. High-Rate Transition Band (Detail) .............................................................................. 30

Figure 16. High-Rate Passband Ripple ......................................................................................... 30

Figure 17. Output Test Load ......................................................................................................... 30

Figure 18. Maximum Loading ........................................................................................................ 30

Figure 19. Power vs. Sample Rate (VA = 5V) ............................................................................... 30

Figure 22. CS43L41 Format 2 ....................................................................................................... 31

Figure 23. CS43L41 Format 3 ....................................................................................................... 32

Figure 24. CS43L41 Format 4 ....................................................................................................... 32

Figure 25. CS43L41 Format 5 ....................................................................................................... 32

Figure 26. CS43L41 Format 6 ....................................................................................................... 33

Figure 27. De-Emphasis Curve ..................................................................................................... 33

Figure 28. ATAPI Block Diagram ..................................................................................................33

LIST OF TABLES

Table 1. Master Clock Divide Enable ............................................................................................... 16

Table 2. Auto-Mute Enable ............................................................................................................... 16

Table 3. Digital Interface Formats .................................................................................................... 17

Table 4. De-emphasis Filter Configurations ..................................................................................... 17

Table 5. Power On/Off Ramp Enable ...............................................................................................18

Table 6. Power Down Enable ........................................................................................................... 18

Table 7. A=B Volume Control Enable............................................................................................... 19

Table 8. Soft Ramp and Zero Cross Enable..................................................................................... 20

Table 9. ATAPI Decode .................................................................................................................... 20

Table 10. Mute Enable ..................................................................................................................... 21

Table 11. Digital Volume Settings .................................................................................................... 22

Table 12. Common Clock Frequencies ............................................................................................ 24