MAS3690CD datasheet(6/41 Pages) DYNEX

6 / 41 page

MA3690/1/3

6/41

REPORT STORE

The report store holds information concerning the success

or failure of the execution of the last instruction, and is

addressed by means of the CODENN, C0 and C1 lines as for

the instruction store The report store is addressed when the R/

WN line is low, the instruction store when the R/WN line is

high.

The report store comprises a Report word, a receive status

word (if applicable) and a transmit status word (if applicable).

The fourth location has no meaning and is not at anytime

addressed.

Word

Report word

RX status word

TX status word

Not used

REPORT WORD

The report word gives the subsystem information as to the

type of error associated with the last transfer (the word will be

clear if no error occurred). The report word is formatted as

follows:

The Report word is written at the end of message

execution, after all retries have been exhausted and prior to

the IRQN line being set active This word indicates the health of

the terminal as well as information relating to the message

execution.

Transmitter Timeout Error

This bit will be set if a transmitter timeout error occurs while

the terminal is transmittting or if a self test on the transmitter

timeout mechanism fails. This will come into effect 800us after

the commencement of the Self Test. The setting of this bit will

also cause a subsystem interrupt to be generated.

This bit will be reset to logic zero if the terminal is reset.

Subsystem Handshake Failure

This bit will be set if the subsystem fails to acknowledge a

terminal request to transfer a data word in 0.75us for a

received data word or 13.5us for a transmit data word. If this

condition takes place while the terminal is transmitting the

transmission will be aborted. The setting of this bit will also

cause a subsystem interrupt to be generated..

This bit will be reset to logic zero if the terminal is reset.

Loop Test Failure

This bit will be set if the receiver circuitry detects an

absence of terminal transmission or a waveform encoding

error occurs while the terminal is transmitting. The seting of

this bit while the terminal is transmitting will cause the

transmission to be aborted and a subsystem interrupt to be

generated.

This bit will be reset to logic zero if the terminal is reset.

Programmed Halt

This bit will be set if the Interrupt Always flag of the

Instruction word has been selected.

This bit will be reset at the start of each new instruction

execution cycle.

Retry Used

This bit will be set if one or more message retries has been

attempted.

This bit will be reset at the start of each new instruction

execution cycle.

Word Count Low

This bit will be set if the terminal detects fewer valid data

words than specified by the Transmit Command word of the

Instruction set.

This bit will be set low at the start of each instruction

execution cycle or message retry.

Word County High

This bit will be set if the terminal detects more valid data

words than specified by the Transmit Command word of the

Instruction set.

This bit will be set low at the start of each instruction

execution cycle or message retry.

Command Error

This bit will be set if an error occurs in the Instruction set.

The setting of this bit will cause instruction execution to be

aborted and a subsystem interrupt to be generated.

This bit will be reset at the start of each new instruction

execution cycle.

15 14 13 12 11 10

Continuous Bus Traffic

TX Timeout Bus 1

TX Timeout Bus 0

RX Status Flag

RX Status Missing

TX Status Flag

TX Status Missing

Command Error

Word Count High

Word Count Low

Retry Used

Programmed Halt

Loop Test Fail

SS Handshake Fail

TX Timeout Error

MAS3690CD 数据表(PDF) 6 Page - Dynex Semiconductor

MAS3690CD 数据表(HTML) 6 Page - Dynex Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表下载

链接网址

MAS3690CD 数据表(PDF) 6 Page - Dynex Semiconductor

MAS3690CD 数据表(HTML) 6 Page - Dynex Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表 下载

链接网址

数据表下载