ADDR10 datasheet(19/68 Pages) ETC2

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System clock an d res e t

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System clock and reset

Signal descriptions

The NS7520 has three clock domains:

System clock (SYSCLK)

Bit rate generation and programmable timer reference clock (XTALA1/2)

System bus clock (BCLK)

The SYS module provides the NS7520 with these clocks, as well as system reset and backup

resources.

This figure shows the timing and specification for RESET_ rise/fall times:

Symbol

I/O

Description

XTALA1

K14

ARM/system oscillator circuit

XTALA2

K12

PLLVDD (1.5V)

L15

PLL clean power

PLLVSS

L12

PLL return

RESET_

A10

System reset

Mnemonic

Signal

Description

XTALA1

XTALA2

Oscillator input

Oscillator output

A standard parallel quartz crystal or crystal oscillator can be

attached to these pins to provide the main input clock to the

NS7520.

PLLVDD

PLLVSS

Clean PLL power

Connect directly to the

GND plane

Power and ground for PLL circuit.

RESET_

System reset

Resets the NS7520 hardware.

Table 2: Clock generation and reset signal description

tR max= 18ns

Vin = 0.8Vto 2.0V

tF max= 18ns

Vin = 2.0Vto 0.8V

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