ADDR10 datasheet(30/68 Pages) ETC2

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AC e l ectrical s p ecificatio ns

NS 75 20 Da ta shee t

03 /2 00 6

Figure 7: System configuration for specified timing

Exceeding the loading shown in Table 7 can result in additional signal delay. The delay can be

approximated by derating the output buffer based on the expected load capacitance per the values

shown in Table 8.

Signal

Estimated load (pF)

Device loads

BCLK

Two SDRAMs, 1 clock buffer/clock

input to PLD

A[27:0], CAS[3:0]_

Two SDRAM An, 1 buffer/PLD

CS[4:0]_

Two SDRAM CSn, 1 buffer PLD

DATA[31:0]

One SDRAM DQ, 1 buffer/PLD

BE*_

One SDRAM DQ, 1 buffer/PLD

TS_, TA_, TEA_, BR_, BG_, BUSY_, WE_,

OE_

1 buffer/PLD

PORTA3, PORTA1, PORTC3, PORTC1

(operating external DMA)

1 buffer/PLD

Other PORTA[*] and PORTC[*], TDO

Tester load

MDC, MDIO, TXEN, TXER, TXD[3:0]

One PHY

Table 7: System loading details

Signal

Derating (ns/pF)

BCLK

0.069

A[27:0], TS_, TA_, TEA_, BR_, BG_, BUSY_, DATA[31:0]

0.150

BE[3:0]

0.300

Table 8: Output buffer derating by load capacitance

SDRAM

NS7520

other

memory

devices

Buffer

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