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ADDR10 数据表(PDF) 35 Page - List of Unclassifed Manufacturers

部件名 ADDR10
功能描述  Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins
PDF  68 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

ADDR10 数据表(HTML) 35 Page - List of Unclassifed Manufacturers

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SR AM ti mi ng
ww w.d i gi .c om
31
SRAM read
CS* controlled read (wait = 2)
Notes:
1
If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock
pulses are required for DMA context switching.
2
Port size determines which byte enable signals are active:
–
8-bit port = BE3*
–
16-bit port = BE[3:0]
–
32-bit port = BE[3:0]
3
The TW cycles are present when the WAIT field is set to 2 or more.
4
The TA* and TEA*/LAST signals are for reference only.
T1
TW
TW
T2
Note-1
T1
12
18
18
28
28
27
27
36
36
6
31
31
30
30
11
10
15
14
Note-2
BCLK
TA* (Note-4)
TEA* (Note-4)
TA* (input)
A[27:0]
BE[3:0]*
CS[4:0]*
read D[31:0]
Sync OE*
CS0OE*
RW*



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