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www.microsemi.com/products/fpga-soc/fpga/igloo-plus

IGLOO PLUS

IGLOO PLUS Devices

I/Os Per Package

IGLOO PLUS Devices

AGLP030

AGLP060

AGLP125

System Gates

30,000

60,000

125,000

Typical Equivalent Macrocells

256

512

1,024

VersaTiles (D-flip-flops)

792

1,584

3,120

Flash*Freeze Mode (typical, µW)

5

10

16

RAM (1,024 bits)

—

18

36

4,608-Bit Blocks

—

4

8

FlashROM Kbits (1,024 bits)

1

1

1

AES-Protected ISP

—

Yes

Yes

—

1

1

6

18

18

I/O Banks

4

4

4

Maximum User I/Os

(packaged device)

120

157

212

Package Pins

CS

VQ

CS201, CS289

VQ128

CS201, CS289

VQ176

CS281, CS289

IGLOO PLUS Devices

AGLP030

AGLP060

AGLP125

I/O Package

Single-Ended I/O

Single-Ended I/O

Single-Ended I/O

CS201

120

157

—

CS281

—

—

212

CS289

120

157

212

VQ128

101

—

—

VQ176

—

137

—

The low power FPGA with enhanced I/O capabilities

IGLOO PLUS products deliver unrivaled low power and I/O features in a feature-rich programmable device, offering up to 64 percent more I/Os than the

award-winning IGLOO products and supporting independent Schmitt trigger inputs, hot-swapping and Flash*Freeze bus hold. Ranging from 30,000 to

125,000 gates, the 1.2 V to 1.5 V IGLOO PLUS devices have been optimized to meet the needs of I/O-intensive, power-conscious applications that require

exceptional features.

• I/O-optimized FPGA

• Ultra low power in Flash*Freeze

mode, as low as 5 µW

• Small footprint and

low-cost packages

• Reprogrammable

flash technology

• 1.2 V to 1.5 V single

voltage operation

• Embedded SRAM NVM

• AES-protected ISP

 Notes:

1. AGLP060 in CS201 does not support the PLL.

2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.

 Note:

* When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by one.