80960KB datasheet(22/44 Pages) INTEL

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80960KB

2.8

AC Specifications

This section describes the AC specifications for the

80960KB pins. All input and output timings are

specified relative to the 1.5 V level of the rising edge

of CLK2. For output timings the specifications refer

to the time it takes the signal to reach 1.5 V.

For input timings the specifications refer to the time

at which the signal reaches (for input setup) or

leaves (for hold time) the TTL levels of LOW (0.8 V)

or HIGH (2.0 V). All AC testing should be done with

input voltages of 0.4 V and 2.4 V, except for the

clock (CLK2), which should be tested with input

voltages of 0.45 V and 0.55 VCC.

Figure 14. Drive Levels and Timing Relationships for 80960KB Signals

1.5V

0.8V

1.5V

VALID OUTPUT

T13

T14

1.5V

VALID OUTPUT

2.0V

0.8V

EDGE

CLK2

OUTPUTS:

LAD 31:0

ADS

W/R, DEN

BE3:0

HLDA

CACHE

LOCK, INTA

ALE

DT/R

INPUTS:

LAD31:0

BADAC

IAC/INT0, INT1

INT2/INTR, INT3

HOLD

LOCK

READY

VALID INPUT

T10

T11

T12

T11

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