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Figure 31. Interrupt Acknowledge Transaction

CLK2

INTR

LAD31:0

ALE

ADS

INTA

DT/R

DEN

LOCK

READY

NOTE:

INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1.

For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted.

INTERRUPT

ACKNOWLEDGEMENT

CYCLE 1

IDLE

(5 BUS STATES)

INTERRUPT

ACKNOWLEDGEMENT

CYCLE 2

PREVIOUS

CYCLE

ADDR

VECTOR

ADDR

CLK