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Contents

FIGURES

Figure 1.

80960KA Programming Environment ........................................................................................ 1

Figure 2.

Instruction Formats .................................................................................................................... 4

Figure 3.

Multiple Register Sets Are Stored On-Chip ............................................................................... 6

Figure 4.

Connection Recommendations for Low Current Drive Network .............................................. 11

Figure 5.

Connection Recommendations for High Current Drive Network .............................................. 11

Figure 6.

Typical Supply Current vs. Case Temperature ......................................................................... 12

Figure 7.

Typical Current vs. Frequency (Room Temp) .......................................................................... 12

Figure 8.

Typical Current vs. Frequency (Hot Temp) ..............................................................................13

Figure 9.

Worst-Case Voltage vs. Output Current on Open-Drain Pins .................................................. 13

Figure 10.

Capacitive Derating Curve ....................................................................................................... 13

Figure 11.

Test Load Circuit for Three-State Output Pins ......................................................................... 14

Figure 12.

Test Load Circuit for Open-Drain Output Pins .......................................................................... 14

Figure 13.

Drive Levels and Timing Relationships for 80960KA Signals .................................................. 16

Figure 14.

Processor Clock Pulse (CLK2) ........................................................................................ ........ 20

Figure 15.

RESET Signal Timing ................................................................................................. ............. 20

Figure 16.

132-Lead Pin-Grid Array (PGA) Package ............................................................................... .21

Figure 17.

80960KA PGA Pinout—View from Bottom (Pins Facing Up) ................................................... 22

Figure 18.

80960KA PGA Pinout—View from Top (Pins Facing Down) .................................................... 23

Figure 19.

80960KA 132-Lead Plastic Quad Flat-Pack (PQFP) Package ................................................ 23

Figure 20.

PQFP Pinout - View From Top ................................................................................................. 24

Figure 21.

HOLD Timing ........................................................................................................................... 30

Figure 22.

16 MHz Maximum Allowable Ambient Temperature ................................................................ 31

Figure 23.

20 MHz Maximum Allowable Ambient Temperature ................................................................ 31

Figure 24.

25 MHz Maximum Allowable Ambient Temperature ................................................................ 32

Figure 25.

Maximum Allowable Ambient Temperature

for the Extended Temperature 80960KA at 20 MHz in PGA Package ...................................... 32

Figure 27.

Burst Read and Write Transaction Without Wait States ........................................................... 34

Figure 28.

Burst Write Transaction with 2, 1, 1, 1 Wait States ..................................................................35

Figure 29.

Accesses Generated by Quad Word Read Bus Request,

Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States) .............................. 36

Figure 30.

Interrupt Acknowledge Transaction ......................................................................................... 37