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STMPE1801 数据表(PDF) 25 Page - STMicroelectronics |
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STMPE1801 数据表(HTML) 25 Page - STMicroelectronics |
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25 / 60 page ![]() STMPE1801 Interrupt system Doc ID 17884 Rev 3 25/60 9.1 Interrupt system register map 9.2 Interrupt latency for the GPIO hot keys When the generation of interrupts by the GPIO as input is enabled for the hot keys, the latency (time taken from actual transition at GPIO to time of INT pin assertion) is shown in the following table: Table 11. Interrupt system register map Address Register name Description Auto-increment (during sequential R/W) 04 INT_CTRL_LOW Interrupt control register Yes 05 INT_CTRL_HIGH Yes 06 INT_EN_MASK_LOW Interrupt enable mask register Yes 07 INT_EN_MASK_HIGH Yes 08 INT_STA_LOW Interrupt status register Yes 09 INT_STA_HIGH Yes 0A INT_EN_GPIO_MASK_LOW Interrupt enable GPIO mask register Yes 0B INT_EN_GPIO_MASK_MID Yes 0C INT_EN_GPIO_MASK_HIGH Yes 0D INT_STA_GPIO_LOW Interrupt status GPIO register Yes 0E INT_STA_GPIO_MID Yes 0F INT_STA_GPIO_HIGH Yes Table 12. GPIO hot keys interrupt latency State of operation Interrupt latency Comments Hibernation >200 µs (default) Latency can be programmed by the GPI_DB bits of SYS_CTRL register Active >200 µs (default) |
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