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STMPE1801 数据表(PDF) 30 Page - STMicroelectronics |
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STMPE1801 数据表(HTML) 30 Page - STMicroelectronics |
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30 / 60 page ![]() Interrupt system STMPE1801 30/60 Doc ID 17884 Rev 3 NT_STA_GPIO Interrupt status GPIO register Address: 0D, 0E, 0F Type: R Reset: 0x00 Description: The interrupt status GPIO register monitors the status of the interruption from a particular GPIO pin interrupt source to the host. The INT_STA_GPIO bits are constantly updated regardless whether the INT_EN_GPIO_MASK bits are enabled or not. The ISG[17:0] bits are the interrupt status bits correspond to the GPIO[17:0] pins. 76 5 4 3 2 1 0 INT_STA_GPIO_LOW ISG7 ISG6 ISG5 ISG4 ISG3 ISG2 ISG1 ISG0 RR R R R R R R 00 0 0 0 0 0 0 15 14 13 12 11 10 9 8 INT_STA_GPIO_MID ISG15 ISG14 ISG13 ISG12 ISG11 ISG10 ISG9 ISG8 RR R R R R R R 00 0 0 0 0 0 0 23 22 21 20 19 18 17 16 INT_STA_GPIO_HIGH Reserved ISG17 ISG16 RR R R R R R R 00 0 0 0 0 0 0 [17:0 ISG[x] Interrupt status GPIO (where x = 17 to 0) ISG[x] will be set to ‘1’ if an interrupt is detected on the corresponding GPIO pin. Reading the INT_STA_GPIO register clears all interrupt status GPIO bits to ‘0’ which had been set to ‘1’ prior to the read event. |
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