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ICS1531 数据表(PDF) 13 Page - Integrated Circuit Systems

部件名 ICS1531
功能描述  Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator
PDF  76 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS1531 数据表(HTML) 13 Page - Integrated Circuit Systems

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Chapter 3
Pin Diagram and Listings
ICS1531 Rev N 12/1/99
December, 1999
13
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
ICS1531 Data Sheet - Preliminary
3.2.3.2
Control Pins
Table 3-4.
Control Pins
Pin
Name
Pin
Type
Pin Description
CLAMP
Input
Clamp.
This pin accepts an external signal that is provided as an alternative to the ICS1531’s
internally generated clamp signal.
PSEL1,
PSEL2,
PSEL3
Output
Programmable Select 1, 2, 3.
These pins are used as general-purpose programmable output pins.
TRESET
Input
Test Reset.
When the ICS1531:
• Is not in Test mode, this pin has no effect.
• Is placed into Test mode:
– This pin acts as a reset that sets the ICS1531 to an initial known state.
– For information about the Test mode, in this table see VSS(TEST).
VSS(TEST)
Input
Ground (Normal Mode) or Test Mode.
• Normal Mode.
For the VSS(TEST) pin’s Normal-mode function, see Table 3-4.
• Test Mode.
– When this pin is connected to either VDDA or VDDAADC, the ICS1531 is in Test
mode. As a result, the ICS1531 is set to an initial known state.
– The Test mode overrides whatever the bit setting of Reg 37:3 is, so that the
Calibration Regs 38h to 3Ch are automatically enabled.
– The Test mode bits are intended for use only by ICS.
VSS(TEST)
ICS1531
In Test mode, Test-mode bits are
enabled and Calibration Regs
38h to 3Ch are automatically
enabled.
VDDA or VDDAADC
Test Mode



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