ICS1531 datasheet(30/76 Pages) ICST

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ICS1531 Rev N 12/1/99

December, 1999

Chapter 6

ICS1531 Data Sheet - Preliminary

6.5.3

The Fdbk Div 0 (Feedback Divider 0) Register, in combination with Fdbk Div 1 Register, sets the value of

the internal feedback divider for the pixel PLL. It adjusts the number of pixel clocks by using the horizontal

total, where:

6.5.4

The Fdbk Div 1 (Feedback Divider 1) Register is used in combination with Fdbk Div 0 Register.

Figure 6-1.

Feedback Divider Modulus

Table 6-5.

Fdbk Div 0 Register

Bit

Bit Name

Bit Definition

Ac-

cess

Spec.

Func.

Re-

set

02:7-

02:0

FDBK [7–0]

(Pixel PLL) Feedback Divider [7-0].

• These bits are the least-significant bits [7-0] for the internal

pixel PLL Feedback Divider. (See Table 6-6 and Figure 6-1,

the Feedback Divider Modulus.)

• When bit 0 is:

– 0 = The total number of pixels is even.

– 1 = The total number of pixels is odd.

R/W

D-PLL

Table 6-6.

Fdbk Div 1 Register

Bit

Bit Name

Bit Definition

Ac-

cess

Spec.

Func.

Re-

set

03:7-

03:4

Reserved

Reserved.

• See Section 6.1, “Reserved Bits”.

• These bits can be programmed to ‘0’.

––

–

03:3-

03:0

FDBK [11-8]

(Pixel PLL) Feedback Divider [11-8].

• These bits are the most-significant bits [11-8] for the internal

pixel PLL Feedback Divider. (See Table 6-5.)

• For the total number of clock periods that the ICS1531

generates between successive HSYNCs, do the following:

–See Figure 6-1.

– Obtain the Feedback Divider Modulus value as follows:

Program the Feedback Divider 0 and Feedback

Divider 1 registers with the total number of horizontal

pixels per line.

Add 8.

Note: The ICS1531 generates 8 more clocks than what is

programmed in these bits.

R/W

D-PLL

Horizontal Total = [(Number of displayed pixels) + (Horizontal blanking interval)] per HSYNC

Fdbk Div 1

(Reg 3)

Fdbk Div 0

(Reg 2)

Feedback Divider Modulus =

+ 8

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