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ICS1531 数据表(PDF) 39 Page - Integrated Circuit Systems

部件名 ICS1531
功能描述  Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator
PDF  76 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS1531 数据表(HTML) 39 Page - Integrated Circuit Systems

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Chapter 6
Register Set
ICS1531 Rev N 12/1/99
December, 1999
39
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
ICS1531 Data Sheet - Preliminary
6.5.19
Register 22h: PNLCLK-SS0
The PNLCLK-SS0 (PNLCLK Spread-Spectrum Counter 0) Register is used in combination with the
PNLCLK-SS1 Register to specify the amount of clock spread. (To select values, see Section 7.3,
“Programming Spread Spectrum”.)
6.5.20
Register 23h: PNLCLK-SS1
The PNLCLK-SS1 (PNLCLK Spread-Spectrum Counter 1) Register is used in combination with the
PNLCLK-SS0 Register. (To select values, see Section 7.3, “Programming Spread Spectrum”.)
Table 6-19.
PNLCLK-SS0 Register
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set
22:7-
22:0
PNLCLK_SS0
[7-0]
PNLCLK Spread-Spectrum (Counter) 0 [7-0].
These bits are the least-significant bits [7-0] for the PNLCLK
spread-spectrum counter.
R/W
D-PK
0
Table 6-20.
PNLCLK-SS1 Register
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set
23:7-
23:4
Reserved
Reserved.
See Section 6.1, “Reserved Bits”.
These bits can be programmed to ‘0’.
––
0
23:3-
23:0
PNLCLK_SS1
[3-0]
PNLCLK Spread-Spectrum (Counter) 1 [3-0].
These bits are the most-significant bits [11-8] for the PNLCLK
spread-spectrum counter.
R/W
D-PK
0



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