| 数据搜索系统,热门电子元器件搜索 |
|
ICS1567 数据表(PDF) 3 Page - Integrated Circuit Systems |
|
|
|||||||||||||||||||||||||||||
ICS1567 数据表(HTML) 3 Page - Integrated Circuit Systems |
|
3 / 11 page ![]() Typical Output Configuration Pin Description PIN NUMBER PIN SYMBOL TYPE DESCRIPTION 1 • FS0 IN Frequency Select LSB. 2 XTAL1 IN Crystal Interface/External Oscillator Input. 3 XTAL2 OUT Crystal Interface. 4 • STROBE IN Control For Frequency Select Latch, also performs automatic RAMDAC reset. 5 VSS -- Device Ground (Both pins must be connected.) 6 VSS -- Device Ground (Both pins must be connected.) 7 LD OUT Load Output. This output is at CLK frequency divided by N1. 8 • FS4 IN Frequency Select MSB. 9 CLK OUT Clock Output Inverted. 10 CLK OUT Clock Output Non-Inverted. 11 VDDO -- Output Stage Power (Both pins must be connected). 12 VDDO -- Output Stage Power (Both pins must be connected). 13 VDD -- PLL System Power. 14 • FS3 IN Frequency Select. 15 • FS2 IN Frequency Select. 16 • FS1 IN Frequency Select. • = inputs with internal pull-up resistor Notes: CLK & CLK outputs are pseudo-ECL. Logic low level is set by the ratio of the resistors stacked across the power supply VLO = (V supply • 160)/(110 +160) in the example shown above. The above values are a good starting point for RAMDAC or clock generator interface. Figure 3 ICS1567 3 |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |