Bus Clock Interface

In some applications, it may be desirable to utilize the bus

clock. To do this, connect the clock through a .047uF capacitor

to XTAL1 (2) and keep the lead length of the capacitor to

XTAL1 (2) to a minimum to reduce noise susceptibility. This

input is internally biased at VDD/2. Since TTL compatible

clocks typically exhibit a VOH of 3.5V, capacitively coupling

the input restores noise immunity. The ICS1567 is not sensitive

to the duty cycle of the bus clock; however, the quality of this

signal varies considerably with different motherboard designs.

As the quality of the bus clock is typically outside the control

of the graphics adapter card manufacturer, it is suggested that

this signal be buffered on the graphics adapter board. XTAL2

(3) must be left open in this configuration.

ICS1567 Interface

The ICS1567 should be located as close as possible to the video

DAC or RAMDAC. Figure 3 illustrates interfacing the

ICS1567 to a RAMDAC. The differential output CLOCK

drivers are current sourcing only and are designed to drive

resistive terminations in a complementary fashion CLK and

CLK connections should follow good ECL interconnection

practice. Terminating resistors should be as close as possible to

the RAMDAC.

Absolute Maximum Ratings

°C to 70°C

±30mA

±50mA

°C to + 150°C

Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against

damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications

Standard Test Conditions

The characteristics below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced

to VSS (OV Ground). Positive current flows into the referenced pin.

Operating Temperature range

0

°C to 70°C

Power supply voltage

4.75 to 5.25 Volts

ICS1567

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