Circuit Description

Overview

The ICS1567 is designed to provide the graphics system clock

signals required by industry standard RAMDACs. One of 32

pre-programmed (user-definable) frequencies may be selected

under digital control. Fully programmable feedback and ref-

erence divider capability allow virtually any frequency to be

generated, not just simple multiples of the reference frequency.

The ICS1567 uses the latest generation of frequency synthesis

techniques developed by ICS and is completely suitable for the

most demanding video applications.

Digital Inputs

The FS0-FS4 pins and the STROBE pin are used to select the

desired operating frequency from the 32 pre-programmed fre-

quencies in the ROM table of the ICS1567. The STROBE pin

also controls activation of the pipeline delay RESET function

included in the ICS1567 (see PIPELINE DELAY RESET

section for details). The FS0-FS4 and STROBE pins are each

equipped with a pull-up and will be at a logic HIGH level when

not connected.

Transparent Mode - When the STROBE pin is held HIGH,

the FS0 through FS4 inputs are transparent; that is, they di-

rectly access the ROM table. The synthesizer will output the

frequency programmed into the location addressed by the

FS0-FS4 pins.

Latched Mode - When the STROBE pin is held LOW, the

FS0-FS4 pins are ignored. The synthesizer will output the

frequency corresponding to the state of the FS0-FS4 pins when

the STROBE pin was last HIGH. In the event that the ICS1567

is powered-up with the STROBE pin held LOW, the synthe-

sizer will output the frequency programmed into address 0 (i.e.,

the one selected with FS0 through FS4 at a logic LOW level).

Frequency Synthesizer Description

Refer to Figure 1 for a block diagram of the ICS1567. The

reference frequency is generated by an on-chip crystal oscilla-

tor, or the reference frequency may be applied to the ICS1567

from an external frequency source.

The ICS1567 generates its output frequencies using phase-

locked loop techniques. The phase-locked loop (or PLL) is a

closed-loop feedback system that drives the output frequency

to be ratiometrically related to the reference frequency provided

to the PLL. The phase-frequency detector shown in the block

diagram drives the VCO to a frequency that will cause the two

inputs to the phase-frequency detector to be matched in fre-

quency and phase. This occurs when:

F(XTAL1)

• Feedback Divider

F(vco) =

Reference Divider

This expression is exact; that is, the accuracy of the output

frequency depends solely on the reference frequency provided

to the part (assuming correctly-programmed dividers). The

divider programming is one of the functions performed by the

ROM look-up table in the ICS1567. The VCO gain is also

ROM programmable which permits the ICS1567 to be opti-

mized for best performance at each frequency in the table.

The feedback divider makes use of a dual-modulus prescaler

technique that allows construction of a programmable counter

to operate at high speeds while still allowing the feedback

divider to be programmed in steps of 1. This is an improvement

over conventional fixed prescaler architectures that typically

impose a factor-of-four penalty (or larger) in this respect.

A post-divider may be inserted between the VCO and the CLK

and CLK outputs of the ICS1567. This is useful in generation

of lower frequencies, as the VCO has been optimized for

high-frequency operation. Different post-divider settings may

be used for each frequency in the table.

ICS1567

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