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ICS2595 数据表(PDF) 3 Page - Integrated Circuit Systems

部件名 ICS2595
功能描述  User-Programmable Dual High-Performance Clock Generator
PDF  12 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS2595 数据表(HTML) 3 Page - Integrated Circuit Systems

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ICS2595
3
Digital Inputs
The FS0-FS3 pins and the STROBE pin are used to select
the desired operating frequency of the VCLK output from
the 16 pre-programmed/user-programmed selections in
the ICS2595. These pins are also used to load new frequency
data into the registers.
The standard interface for the ICS2595 matches the interface
of the industry standard ICS2494. That is, the FS0-FS3
inputs access the device internals transparently when the
STROBE pin is high.
The digital interface for the ICS2595 (i.e. the FS0-FS3
inputs) may be optionally configured for edge-triggered
or level-activated operation of the STROBE pin. Example
timing requirements for each of the four options are
shown in Figure 1.
The programming sequence has been designed in such a
way that STROBE pin need not be used (as in situations
where the device is connected to the frequency select port
of some VGA chips).
VCLK Output Frequency Selection
To change the VCLK output frequency, simply write the
appropriate data to the ICS2595 FS inputs. The synthesizer
will output the new frequency programmed into that location
after a brief delay (see time-out specifications).
Upon device power-up, the selected frequency will be the
frequency pre-programmed into address 0 until a device
write is performed.
MCLK Output Frequency Selection
The MS0-MS1 pins are used to directly select the desired
operating frequency of the MCLK output from the four
pre-programmed/user-programmed
selections
in
the
ICS2595. These inputs are not latched, nor are they involved
with memory programming operations.
Programming Mode Selection
In order to ensure that reliable programming under all
circumstances, we require that two "nibble" writes be
added to the beginning of the programming sequence that
was previously specified. The new sequence is shown in
Table 1. Note that the FS3 data is "0" for these first two
writes.
e
l
b
b
i
N
0
S
F1
S
F2
S
F3
S
F
1X
X
0
0
2X
X
1
0
3X
X
)
"
0
"
e
b
t
s
u
m
(
ti
b
T
R
A
T
S0
4X
X
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1
5X
X
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b
t
s
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m
(
ti
b
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r
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W
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R
)
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0
"
0
6X
X
"
1
7X
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)
B
S
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n
o
it
a
c
o
l
(
O
L0
8X
X
"
1
9X
X
1
L0
0
1X
X
"
1
1
1X
X
2
L0
2
1X
X
"
1
3
1X
X
3
L0
4
1X
X
"
1
5
1X
X
)
B
S
M
n
o
it
a
c
o
l
(
4
L0
6
1X
X
"
1
7
1X
X
B
S
L
k
c
a
b
d
e
e
f
(
0
N0
8
1X
X
"
1
9
1X
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1
N0
0
2X
X
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1
1
2X
X
2
N0
2
2X
X
"
1
3
2X
X
3
N0
4
2X
X
"
1
5
2X
X
4
N0
6
2X
X
"
1
7
2X
X
5
N0
8
2X
X
"
1
9
2X
X
6
N0
0
3X
X
"
1
1
3X
X
)
B
S
M
k
c
a
b
d
e
e
f
(
7
N0
2
3X
X
"
1
3
3X
X
)
"
1
"
fi
t
c
e
l
e
s
(
Q
E
R
F
T
X
E0
4
3X
X
"
1
5
3X
X
)
B
S
M
r
e
d
v
i
d
-
t
s
o
p
(
0
D0
6
3X
X
"
1
7
3X
X
)
B
S
M
r
e
d
v
i
d
-
t
s
o
p
(
1
D0
8
3X
X
"
1
9
3X
X
)
"
1
"
e
b
t
s
u
m
(
ti
b
1
P
O
T
S0
0
4X
X
"
1
1
4X
X
)
"
1
'
e
b
t
s
u
m
(
ti
b
2
P
O
T
S0
2
4X
X
"
1
Table 1: Programming Sequence
Because the same pins are used for both VCLK frequency
selection and re-programming the device frequency table,
a specific procedure must be observed for selection between
these modes. Device programming is accomplished by
executing a "programming sequence". The latched FS2
input functions as a data input, and the latched FS3 input
functions as a data clock when this mode is activated. As
the latched FS3 data transitions from 0 to 1, the latched
FS2 data is shifted into the register. Note that it is the



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