4

ICS2595

LATCHED FS inputs, not the FS inputs themselves, that

are interpreted by the internal logic. Interface logic resides

between the FS input pins and the programming/frequency

select logic. The appropriate "data write" procedure must

be observed. See the section "Digital Interface" in this

supplement for more information.

These rules must be followed:

•

reference frequency in Hz) by the following formulas:

•

A programming sequence consists of 42 successive

data writes to the device as shown in table 1: no delay

any two successive writes.

•

A readback sequence consists of 64 successive data

writes to the device as shown in table 2: no delay

any two successive writes.

•

Programming or readback sequences must be preceded

writes to the device unless it was immediately preceded

by another legal programming (or readback) sequence

(nothing else in between)

•

To change the active VCLK frequency selection, simply

write that data to the device; the last data written to the

part will always become VCLK frequency select after

register is cleared at this time also.

The FS0 & FS1 inputs are not used for programming, so it

is possible to use a two-pin interface for programming and

frequency selection (any bank of four VCLK addresses).

The reference frequency source must be operational for

proper execution of the programming sequence. If the on-

device has valid power before attempting to program it.

Data Description

Location Bits (l0-L4)

The first five bits after the start bit control the frequency

location to be re-programmed according to this table. The

rightmost bit (the LSB) of the five shown in each

selection of the table is the first one sent.

)

0

.

4

(

LN

O

I

T

A

C

O

L

0

0

0

0

00

s

s

e

r

d

d

A

K

L

C

V

1

0

0

0

01

s

s

e

r

d

d

A

K

L

C

V

0

1

0

0

02

s

s

e

r

d

d

A

K

L

C

V

1

1

0

0

03

s

s

e

r

d

d

A

K

L

C

V

0

0

1

0

04

s

s

e

r

d

d

A

K

L

C

V

1

0

1

0

05

s

s

e

r

d

d

A

K

L

C

V

0

1

1

0

06

s

s

e

r

d

d

A

K

L

C

V

1

1

1

0

07

s

s

e

r

d

d

A

K

L

C

V

0

0

0

1

08

s

s

e

r

d

d

A

K

L

C

V

1

0

0

1

09

s

s

e

r

d

d

A

K

L

C

V

0

1

0

1

00

1

s

s

e

r

d

d

A

K

L

C

V

1

1

0

1

01

1

s

s

e

r

d

d

A

K

L

C

V

0

0

1

1

02

1

s

s

e

r

d

d

A

K

L

C

V

1

0

1

1

03

1

s

s

e

r

d

d

A

K

L

C

V

0

1

1

1

04

1

s

s

e

r

d

d

A

K

L

C

V

1

1

1

1

05

1

s

s

e

r

d

d

A

K

L

C

V

0

0

0

0

10

s

s

e

r

d

d

A

K

L

C

M

1

0

0

0

11

s

s

e

r

d

d

A

K

L

C

M

0

1

0

0

12

s

s

e

r

d

d

A

K

L

C

M

1

1

0

0

14

s

s

e

r

d

d

A

K

L

C

M

Table 3 - Location Bit Programming

Feedback Set Bits (N0-N7)

These bits control the feedback divider setting for the

location specified. The modulus of the feedback divider

will be equal to the value of these bits + 257. The least

significant bit (N0) is sent first.

Post-Divider Set Bits (D0-D1)

These bits control the post-divider setting for the location

specified according to this table. The least significant bit

(D0) is sent first.

Table 4 - Post-Divider Programming

)

0

-

1

(

DR

E

D

I

V

I

D

-

T

S

O

P

0

08

1

04

0

12

1

11

6* R

4096* R