Integrated

Circuit

Systems, Inc.

User-Programmable Dual High-Performance Clock Generator

ICS2595

Pin Configuration

Block Diagram

ICS2595 RevB 3/2/00

20-Pin DIP or SOIC

Features

•

Advanced ICS monolithic phase-locked loop

technology for extremely low jitter

•

Supports high-resolution graphics - VCLK

output to 145 MHz

•

Completely integrated - requires only external

crystal (or reference frequency and decoupling)

•

Power-down modes support portable computing

•

Sixteen selectable VCLK frequencies

(all user re-programmable)

•

Four selectable MCLK frequencies

(all user re-programmable)

Description

The ICS2595 is a dual-PLL (phase-locked loop) clock

generator specifically designed for high-resolution, high-

refresh rate, video applications. The video PLL generates

any of 16 pre-programmed frequencies through selection

of the address lines FS0-FS3. Similarly, the auxiliary PLL

can generate any one of four pre-programmed frequencies

via the MS0 & MS1 lines.

A unique feature of the ICS2595 is the ability to redefine

frequency selections in both the VCLK and MCLK synthesiz-

ers after power-up. This permits complete set-up of the

frequency table upon system initialization.

Applications

•

PC Graphics

•

VGA/Supper VGA/XGA Applications

Not recommended for new designs