ICS2595

5

Read/Write* Control Bit

When set to a “0,” the ICS2595 shift register will transfer its

contents to the selected memory register at the completion

of the programming sequence.

When this bit is a “1,” the selected memory location will be

transferred to the shift register to permit a subsequent readback

of data. No modification of device memory will be performed.

"Readback" of a location in the frequency table may be

performed by execution the 64 step readback sequence. The

readback sequence is shown in Table 2. Note that the readback

sequence is essentially the programming sequence (with the

R/W* bit set high) followed by the actual data readback.

The bi-directional FS0 pin will convert to output mode after

the 42nd nibble write and the logic level output will be that

of the first data bit (N0). Subsequent "clocking" by latching

FS3 to "0" and then to "1" will shift out the remaining data

bits. The last two writes will return the FS0 pin to input

mode.

EXTFREQInput

The EXTFREQ input allows an externally generated fre-

quency to be routed to the VCLK or MCLK output pins

under device programming control. If the EXTFREQ bit is

set (logic “1”) at the selected address location, the frequency

applied to the EXTFREQ input will be routed to the output

instead of the frequency generated by the VCLK (or MCLK)

PLL.

When setting the EXTFREQ bit to a “1,” be sure that the D0

and D1 bits are not both set to “1” also, unless it is intended

that the phase-locked loop be shutdown as well.

PowerConservation

The ICS2595 supports power conservation by permitting

either or both of the phase-locked loops to be disabled. This

can be done by programming a particular address to have

EXTFREQ, D0, & D1 bits set to a logic “1.” Any frequency

applied to the EXTFREQ pin will still be passed through the

output multiplexer and appear at the respective output.The

crystal oscillator is not affected by this power-down function

and will continue to operate normally.

Frequency Synthesizer Description

Refer to the block diagram of the ICS2595. The ICS2595

generates its output frequencies using phase-locked loop

techniques. The phase-locked loop (or PLL) is a closed-loop

feedback system that drives the output frequency to be

ratiometrically related to the reference frequency pro-vided

to the PLL. The phase-frequency detector shown in the

block diagram drives the VCO to a frequency that will cause

the two inputs to the phase-frequency detector to be matched

in frequency and phase. This occurs when:

where N is the effective modulus of the feedback divider

chain and R is the modulus of the reference divider chain.

The feedback divider on the ICS2595 may be set to any

integer value from 257 to 512. This is done by the setting of

the N0-N7 bits. The standard reference divider on the ICS2595

is fixed to a value of 43 (this may be set to a different value

via ROM programming; contact factory). The ICS2595 is

equipped with a post-divider and multiplexer that allows

the output frequency range to be scaled down from that of

the VCO by a factor of 2, 4, or 8,

therefore, the VCO frequency range will be from 5.976 to

11.906 (257/43 to 512/43) of the reference frequency. The

output frequency range will be from 0.747 to 11.906 times

the reference frequency. Worst case accuracy for any desired

fre-quency within that range will be 0.2%.

If a 14.31818 MHz reference is used, the output frequency

range would be from 10.697 MHz to 170.486 MHz (but the

upper end is first limited to 145 MHz by the ICS2595 output

driver).

Programming Example

Suppose that we want differential CLK output to be 45.723

MHz. We will assume the reference frequency to be 14.31818

MHz.

The VCO frequency range will be 85.565 MHz to 170.486

MHz (5.976 * 14.31818 to 11.906 * 14.31818). We will

need to set the post-divider to two to get an output of 45.723

MHz.

The VCO will then need to be programmed to two times

45.723 MHz, or 91.446 MHz. To calculate the required feed-

N

R