ICS570B

Multiplier and Zero Delay Buffer

MDS 570B A

3

Revision 053001

Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com

PRELIMINARY INFORMATION

Electrical Specifications

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (Note 1)

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage, VDD

Referenced to GND

7

V

Inputs

Referenced to GND

-0.5

VDD+0.5

V

Clock Output

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

ICS570B

0

70

°C

ICS570BI

-40

85

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 3.3V)

DC CHARACTERISTICS (VDD = 3.3V)

Operating Voltage, VDD

3.15

3.45

V

Input High Voltage, VIH

ICLK, FBIN

2

V

Input Low Voltage, VIL

ICLK, FBIN

0.8

V

Input High Voltage, VIH

S0, S1

VDD-0.5

V

Input High Voltage, VIM (mid-level)

S0, S1

VDD/2

V

Input Low Voltage, VIL

S0, S1

0.5

V

Output High Voltage, VOH, CMOS level

IOH=-4mA

VDD-0.4

V

Output High Voltage, VOH

IOH=-12mA

2.4

V

Output Low Voltage, VOL

IOL=12mA

0.4

V

IDD Operating Supply Current, 50 in, 100 out

No Load, 3.3V

16

mA

Short Circuit Current

Each Output

±100

mA

Input Capacitance, S1, S0

5

pF

AC CHARACTERISTICS (VDD = 3.3V)

AC CHARACTERISTICS (VDD = 3.3V)

Input Frequency, ICLK (see table on page 2)

FBIN from CLK/2

See Table on Page 2

See Table on Page 2

See Table on Page 2

Output Clock Frequency, CLK

10

150

MHz

Output to output skew

Note 2

100

175

ps

Input to Output Jitter

40-150 MHz

100-250

ps

Input skew, ICLK to FBIN Note 2

CLK>30MHz

-300

300

ps

Input skew, ICLK to FBIN Note 2

VDD=3.3V, CLK<10MHz

-600

600

ps

Output Clock Rise Time, 3.3V

0.8 to 2.0V, note 3

0.75

ns

Output Clock Fall Time, 3.3V

2.0 to 0.8V, note 3

0.75

ns

Output Clock Duty Cycle

at VDD/2

45

49 to 51

55

%

Notes

1. Stresses beyond these can permanently damage the device

2. Assumes clocks with same rise time, measured from rising edges at VDD/2.

3. With 27

Ω terminating resistor and 15 pF loads.