ICS570B

Multiplier and Zero Delay Buffer

MDS 570B A

5

Revision 053001

Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com

PRELIMINARY INFORMATION

Recommended Circuit:

VDD

GND

INPUT

ICK

CLK

CLK/2

ICLK

CLK

CLK/2

x2 Mode (S1, S0 = 1, 1)

CLK Feedback

x2 Mode (S1, S0 = 1, 0)

CLK/2 Feedback

CLK

CLK/2

S1

S0

Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK. However, the CLK/2

could be a falling edge compared with ICLK. Therefore, whenever possible, we recommend the use of CLK/2 feedback.

This will synchronize the rising edges of all 3 clocks.

FBIN