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80960KB 数据表(PDF) 21 Page - Intel Corporation |
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80960KB 数据表(HTML) 21 Page - Intel Corporation |
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21 / 39 page ![]() 80960KB 20 Figure 15. Processor Clock Pulse (CLK2) Figure 16. RESET Signal Timing HIGH LEVEL (MIN) 0.55VCC LOW LEVEL (MAX) 0.8V T1 T3 T5 T4 T2 90% 10% 1.5 V ... ... ... ... CLK2 CLK RESET OUTPUTS FIRST A B C D A INIT PARAMETERS (BADAC, INT0/IAC) MUST BE SET UP 8 CLOCKS PRIOR TO THIS CLK2 EDGE INIT PARAMETERS MUST BE HELD BEYOND THIS CLK2 EDGE T15 = RESET HOLD T16 = RESET SETUP T17 = RESET WIDTH T15 T16 T17 |
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