Data Sheet

AD5543/AD5553

Rev. F | Page 9 of 20

CIRCUIT OPERATION

The AD5543/AD5553 contain 16-/14-bit current output, DACs,

serial input registers, and DAC registers. Both converters use a

3-wire serial data interface.

DAC SECTION

The DAC architecture uses a current steering R-2R ladder

design. Figure 18 shows the typical equivalent DAC structure.

The DAC contains a matching feedback resistor for use with an

external op amp (see Figure 19). With RFB and IOUT terminals

connected to the op amp output and inverting node, respectively,

a precision voltage output is achieved as

(1)

(2)

polarity for dc reference voltages.

These DACs are designed to operate with either negative or

by the internal logic to drive the on and off states of the DAC

switches.

R

R

R

GND

2R

2R

2R

S1

S2

DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY;

5kΩ

R

Figure 18. Equivalent R-2R DAC Circuit

Note that a matching switch is used in series with the internal

GND

SCLK SDIN

R1

SYNC

AD5543/

AD5553

AGND

C1

A1

R2

µCONTROLLER

NOTES

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. C1 PHASE COMPENSATION (4pF TO 6pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 19. Voltage Output Configuration

These DACs are also designed to accommodate ac reference

input signals. The AD5543 accommodates input reference

voltages in the range of −12 V to +12 V. The reference voltage

inputs exhibit a constant nominal input resistance value of 5 kΩ

various resistances and capacitances. External amplifier choice

should take into account the variation in impedance generated

by the AD5543 on the inverting input node of the amplifier.

The feedback resistance, in parallel with the DAC ladder

resistance, dominates output voltage noise. To maintain good

analog performance, power supply bypassing of 0.01 µF to 0.1 µF

ceramic or chip capacitors, in parallel with a 1 µF tantalum

capacitor, is recommended. Due to degradation of PSRR in

frequency, users must avoid using switching power supplies.