Data Sheet

AD5543/AD5553

Rev. F | Page 11 of 20

APPLICATIONS INFORMATION

STABILITY

U2

U1

AD5543/AD5553

GND

AD8628

C1

Figure 21. Optional Compensation Capacitor for Gain Peaking Prevention

node of the op amp must be connected as close as possible to

each other, and proper PCB layout technique must be employed.

Because every code change corresponds to a step function, gain

peaking may occur if the op amp has limited GBP and there is

excessive parasitic capacitance at the inverting node.

An optional compensation capacitor, C1, can be added for

stability, as shown in Figure 21. C1 should be found empirically,

but 20 pF is generally adequate for the compensation.

POSITIVE VOLTAGE OUTPUT

To achieve the positive voltage output, an applied negative

reference to the input of the DAC is preferred over the output

inversion through an inverting amplifier because of the tolerance

errors of the resistors. To generate a negative reference, the

reference can be level-shifted by an op amp such that the VOUT

and GND pins of the reference become the virtual ground and

−2.5 V, respectively (see Figure 22).

U2

U1

AD5543/AD5553

GND

1/2AD8628

1/2AD8620

GND

V+

V–

+5V

–5V

ADR03

+5V

–2.5V

U3

U4

C1

Figure 22. Positive Voltage Output Configuration

BIPOLAR OUTPUT

The AD5543/AD5553 are inherently 2-quadrant multiplying

DACs. That is, they can easily be set up for unipolar output

operation. The full-scale output polarity is the inverse of the

reference input voltage.

In some applications, it may be necessary to generate the full

4-quadrant multiplying capability or a bipolar output swing,

which is easily accomplished by using an additional U4 external

amplifier configured as a summing amplifier (see Figure 23). In

this circuit, the second amplifier, U4, provides a gain of 2 that

increases the output span magnitude to 5 V. Biasing the external

amplifier with a 2.5 V offset from the reference voltage results in a

full 4-quadrant multiplying circuit. The transfer equation of this

circuit shows that both negative and positive output voltages are

created as the input data (D) is incremented from code zero

+2.5 V).

(3)

(4)

For the AD5543, the resistance tolerance becomes the dominant

error of which users should be aware.

U2

U1

AD5553 ONLY

GND

1/2AD8620

GND

ADR03

U3

1/2AD8620

V+

V–

+5V

–5V

+5V

U4

C1

C2

R3

R1

10k

Ω ± 0.01%

5k

Ω ± 0.01%

10kΩ ± 0.01%

+5V

R2

Figure 23. 4-Quadrant Multiplying Application Circuit