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AD5553 数据表(PDF) 3 Page - Analog Devices

部件名 AD5553
功能描述  Current Output/Serial Input, 16-/14-Bit DACs
PDF  20 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5553 数据表(HTML) 3 Page - Analog Devices

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Data Sheet
AD5543/AD5553
Rev. F | Page 3 of 20
SPECIFICATIONS
VDD = 5 V ± 10%, VSS = 0 V, IOUT = virtual GND, GND = 0 V, VREF = 10 V, TA = full operating temperature range, unless otherwise noted.
Table 1.
Parameter
Symbol
Condition
5 V ± 10%
Unit
STATIC PERFORMANCE1
Resolution
N
1 LSB = VREF/216 = 153 µV when VREF = 10 V (AD5543)
16
Bits
1 LSB = VREF/214 = 610 µV when VREF = 10 V (AD5553)
14
Bits
Relative Accuracy
INL
Grade: AD5553C
±1
LSB max
Grade: AD5543C
±1
LSB max
Grade: AD5543B
±2
LSB max
Differential Nonlinearity
DNL
Monotonic
±1
LSB max
Output Leakage Current
IOUT
Data = 0x0000, TA = 25°C
10
nA max
Data = 0x0000, TA = TA maximum
20
nA max
Full-Scale Gain Error
GFSE
Data = 0xFFFF
±1/±4
mV typ/max
Full-Scale Temperature Coefficient2
TCVFS
1
ppm/°C typ
REFERENCE INPUT
VREF Range
VREF
−15/+15
V min/max
Input Resistance
RREF
5
kΩ typ3
Input Capacitance2
CREF
5
pF typ
ANALOG OUTPUT
Output Current
IOUT
Data = 0xFFFF for AD5543
2
mA typ
Data = 0x3FFF for AD5553
Output Capacitance2
COUT
Code dependent
200
pF typ
LOGIC INPUTS AND OUTPUT
Logic Input Low Voltage
VIL
0.8
V max
Logic Input High Voltage
VIH
2.4
V min
Input Leakage Current
IIL
10
µA max
Input Capacitance2
CIL
10
pF max
INTERFACE TIMING2, 4
See Figure 4 and Figure 5
Clock Input Frequency
fCLK
50
MHz
Clock Width High
tCH
10
ns min
Clock Width Low
tCL
10
ns min
CS to Clock Setup
tCSS
0
ns min
Clock to CS Hold
tCSH
10
ns min
Data Setup
tDS
5
ns min
Data Hold
tDH
10
ns min
SUPPLY CHARACTERISTICS
Power Supply Range
VDD RANGE
4.5/5.5
V min/max
Positive Supply Current
IDD
Logic inputs = 0 V
10
µA max
Power Dissipation
PDISS
Logic inputs = 0 V
0.055
mW max
Power Supply Sensitivity
PSS
ΔVDD = ±5%
0.006
%/% max



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