AD9953_15 datasheet(19/32 Pages) AD

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AD9953

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s 0x05)

put

ent

ct pins PS<1:0>.

ial

to the ending address.

e the serial port to expect

bit words. The first 32 bits would be parsed as a word

n).

ase

-tone FSK, the user programs each RAM segment

e adder (<31:18>).

dest

irect

odes that enable the memory,

bit controls whether the RAM output

ulator or the phase offset adder.

r finishes a cycle, the RAM address generator

crements to the next address and the timer reloads the ramp

te bits and begins a new countdown cycle. This sequence

ontinues until the RAM address generator has incremented to

n address equal to the RAM segment final address bits of the

urrent RSCW.

input of the phase accumulator and supplies the frequency

tuning word(s) for the device. When the RAM output drives the

phase accumulator, the phase offset word (POW, Addres

drives the phase-offset adder. Similarly, when the RAM out

drives the phase offset adder, the frequency tuning word (FT

Address 0x04) drives the phase accumulator. When CFR1<31>

is Logic 0, the RAM is inactive unless being written to via the

serial port. The power-up state of the AD9953 is the single-tone

mode, in which the RAM enable bit is inactive. The RAM is

segmented into four unique slices controlled by the Profile<1:0

input pins.

rolled

RAM Controlled Modes of Operation

Direct Switch Mode

Direct switch mode enables FSK or PSK modulation. The

AD9953 is programmed for direct switch mode by writing the

RAM enable bit true and programming the RAM segment

mode control bits of each desired profile to Logic 000(b). This

mode simply reads the RAM contents at the RAM segment

beginning address for the current profile. No address ramping is

enabled in direct switch mode.

To perform 4

All RAM writes/reads, unless otherwise specified, are cont

by the Profile<1:0> input pins and the respective RAM segm

control word. The RAM can be written to during normal

operation, but any I/O operation that commands the RAM to be

written immediately suspends read operation from the RA

causing the current mode of operation to be nonfunctional. Thi

excludes single-tone mode, as the RAM is not read in this mode

Writing the RAM is accomplished as follows. After configuring

the desired RAM segment control words, the desired RAM

segment must be selected via the profile sele

During the instruction byte, write the address for the RAM,

0x0B. The serial port and RAM controller will work in

conjunction to determine the width of the profile and the ser

port will accept the defined number of 32-bit words

sequentially from the beginning address

Consider the following example:

•

The RAM Segment Control Word 1 lists the beginning

RAM address at 256 and the ending address at 511.

•

PS0 = 1 and PS1 = 0.

•

The instruction byte is 10001001.

The RAM controller would configur

256 32-

and sent to RAM Address 256. The next 32 bits would be pars

and sent to 257, and so forth, all the way through until the 256

word was sent (grand total of 8,192 data bits in this operatio

MODES OF OPERATION

Single-Tone Mode

In single-tone mode, the DDS core uses a single tuning word.

Whatever value is stored in FTW0 is supplied to the phase

accumulator. This value can only be changed manually, which is

done by writing a new value to FTW0 and by issuing an I/O

UPDATE. Phase adjustment is possible through the ph

offset registe

ontrol word for direct switch mode and a unique beginning

address value. In addition, the RAM enable bit is written true,

which enables the RAM, and the RAM destination bit is written

false, setting the RAM output to be the frequency tuning word.

The Profile<1:0> inputs are the 4-tone FSK data inputs. When

the profile is changed, the frequency tuning word stored in the

new profile is loaded into the phase accumulator and is used to

increment the currently stored value in a phase continuous

fashion. The phase offset word drives the phase-offset adder.

Two-tone FSK is accomplished by using only one profile pin f

data.

Programming the AD9953 for PSK modulation is similar to

FSK except the RAM destination bit is set to a Logic 1, enabling

the RAM output to drive the phase offset adder. The FTW0

drives the input to the phase accumulator. Toggling the profile

pins changes (modulates) the current phase value. The upper

14 bits of the RAM drive the phas

Bit <17:0> of the RAM output are unused when the RAM

ination bit is set. The no-dwell bit is a Don’t Care in d

sw ch mode.

Ra p-Up Mode

Ramp-up mode, in conjunction with the segmented RAM

capability, allows up to four different sweep profiles to be

programmed into the AD9953. The AD9953 is programmed for

ramp-up mode by writing the RAM enable bit true and

programming the RAM mode control bits of each profile to be

used to Logic 001(b). As in all m

the RAM destination

drives the phase accum

Upon starting a sweep (via an I/O UPDATE or change in

profile bits), the RAM address generator loads the RAM

segment beginning address bits of the current RSCW, driving

the RAM output from this address, and the ramp rate timer

loads the RAM segment address ramp rate bits. When the

ramp rate time

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