AD9953_15 datasheet(22/32 Pages) AD

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AD9953

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trol.

ter

utput signal is offset

y a constant angle relative to the nominal signal. This allows

put with some external

d meth

here the user regularly

tes the phas

port. By properly

ifying the ph

implement a pha

However, both the

of the I/O

rate at which pha

allo

hase accum

automatic zeroin

olled via th

phase

mulator bit.

holds the value t

tinuous Cle

he continuous clear bit is simply a static control signal that,

s the

-off

r value into the amplitude scale factor (ASF) register.

he shaped on-off keying function may be bypassed (disabled)

by clearing the OSK enable bit (CFR1<25> = 0).

e most signifi-

unction register (CFR). CFR1<25> is

tive

ode

Off Keying Mode Operation

termined

he OSK

all 0s

he DDS core output by 16383 (decimal).

nally generated scale factor step size

<15:14> bits. Table 8 describes the

ts of the amplitude

he user to ramp to a value less

PROGRAMMING AD9953 FEATURES

Phase Offset Control

A 14-bit phase offset (θ) may be added to the output of the phase

accumulator by means of the control registers. This feature

provides the user with two different methods of phase con

The first method is a static phase adjustment where a fixed

phase offset is loaded into the appropriate phase offset regis

and left unchanged. The result is that the o

the user to phase align the DDS out

a .

signal, if necess

The secon

od of phase control is w

upda

e offset register via the I/O

mod

ase offset as a function of time, the user can

se modulated output signal.

speed

port and the frequency of SYSCLK limit the

se modulation can be performed.

The AD9953

ws for a programmable continuous zeroing o

the p

ulator as well as a clear and release or

g function. Each feature is individually

contr

e CFR1 bits. CFR1<13> is the automatic clear

accu

CFR1<10> clears the phase accumulator and

o zero.

Con

ar Bit

when active high, holds the phase accumulator at zero for the

entire time the bit is active. When the bit goes low, inactive, the

phase accumulator is allowed to operate.

Clear and Release Function

When set, the auto-clear phase accumulator clears and releases

the phase accumulator upon receiving an I/O UPDATE. The

automatic clearing function is repeated for every subseque

I/O UPDATE until the appropriate auto-clear control bit is

cleared.

Shaped On-Off Keying

The shaped on-off keying function of the AD9953 allow

user to control the ramp-up and ramp-down time of an on

emission from the DAC. This function is used in burst

transmissions of digital data to reduce the adverse spectral

impact of short, abrupt bursts of data.

Auto and manual shaped on-off keying modes are supporte

The auto mode generates a linear scale factor at a rate

determined by the amplitude ramp rate (ARR) register

controlled by an external pin (OSK). Manual mode allows t

user to directly control the output amplitude by writing the

scale facto

The modes are controlled by two bits located in th

cant byte of the control f

the shaped on-off keying enable bit. When CFR1<25> is set, th

output scaling function is enabled and CFR1<25> bypasses the

function. CFR1<24> is the internal shaped on-off keying ac

bit. When CFR1<24> is set, internal shaped on-off keying m

is active; CFR1<24> is cleared, external shaped on-off keying

mode is active. CFR1<24> is a Don’t Care if the shaped on-off

keying enable bit (CFR1<25>) is cleared. The power-up

condition is shaped on-off keying disabled (CFR1<25> = 0).

Figure 20 shows the block diagram of the OSK circuitry.

AUTO Shaped On-

The auto shaped on-off keying mode is active when CFR1<25>

and CFR1<24> are set. When auto shaped on-off keying mode

is enabled, a single scale factor is internally generated and

applied to the multiplier input for scaling the output of the DDS

core block (see Figure 20). The scale factor is the output of a

14-bit counter that increments/decrements at a rate de

by the contents of the 8-bit output ramp rate register. The scale

factor increases if the OSK pin is high and decreases if t

pin is low. The scale factor is an unsigned value such that

multiply the DDS core output by 0 (decimal) and 0x3FFF

multiplies t

For those users who use the full amplitude (14 bits) but need

fast ramp rates, the inter

is controlled via the ASF

increment/decrement step size of the internally generated scal

factor per the ASF<15:14> bits.

A special feature of this mode is that the maximum output

amplitude allowed is limited by the conten

scale factor register. This allows t

than full scale.

Table 8. Auto-Scale Factor Internal Step Size

ASF<15:14> (Binary)

Increment/Decrement Size

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