AD9953_15 datasheet(21/32 Pages) AD

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AD9953

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fied RAM

Notes

next address, and the timer reloads the ramp rate bits and

continues counting down. This sequence continues until the

RAM address generator has incremented to an address equal to

the RAM segment final address bits of the current RSCW. Upo

reaching this terminal address, the RAM address generator

reloads the RAM segment beginning address bits and the

sequence repeats.

The sequence of circulating through the speci

addresses repeats for as long as the part is programmed for th

mode. The no-dwell bit is a Don’t Care in this mode.

RAM Controlled Modes of Operation Notes and

Summary

Notes:

The user must ensure that the beginning address is lowe

than the final address.

Changing profiles or issuing an I/O UPDATE automatically

terminates the current sweep and starts the next sweep.

Setting the RAM destination bit true such that the RAM

output drives the phase offset adder is valid. While the

above discussion describes a frequency sweep, a phase

sweep operation is also available.

The AD9953 offers five modes of RAM controlled operation

(see Table 6).

Table 6. RAM Modes of Operation

RSCW<7:5>

(Binary)

Mode

000

Direct Switch

No Sweeping, P

Valid, No Dwell Invalid

rofiles

001

Ramp Up

Sweeping, Profiles Valid,

No Dwell Valid

010

Bidirectional

Ramp

Sweeping, Profile <0>

Direction Control Bit, N

Dwell Invalid

Is a

011

Continuous

Bidirectional

Ramp

Sweeping, Profiles V

No Dwell Invalid

alid,

100

Continuous

Recirculate

Sweeping, Profiles Valid

No Dwell Invalid

101, 110, 111

Open

Invalid Mode—Default To

Direct Switch

Internal Profile Control

The AD9953 offers a mode in which a composite frequency

sweep can be built, for which the timing control is software

here

AM address generator has exhausted the

Mode Description

programmable. The internal profile control capability disen-

gages the Profile<1:0> pins and enables the AD9953 to take

control of switching between profiles. Modes are defined that

allow continuous or single burst profile switches for three

combinations of profile selection bits. These are listed in

Table 7. When any of the CFR1<29:27> bits are active, the

internal profile control mode is engaged. Internal profile control

is only valid when the device is operating in RAM mode. T

is no internal profile control for linear sweeping operations.

When the internal profile control mode is engaged, the RAM

segment mode control bits are Don’t Care and the device

operates all profiles as if these mode control bits were

programmed for ramp-up mode. Switching between profile

occurs when the R

memory contents for the current profile.

Table 7. Internal Profile Control

CFR1<29:27>

(Binary)

000

Internal Control Inactive

001

Internal Control Active, Single Burst, Activate

Profile 0, Then 1, Then Stop

010

Internal Control Active, Single Burst, Activate

Profile 0, Then 1, Then 2, Then Stop

011

Internal Control Active, Single Burst, Activa

Profile 0, Then 1, Then 2, Then 3, Then Stop

100

Internal Control Active, Continuous, Activate

Profile 0, Then 1, Then Loop Starting 0

101

, Then Loop Starting 0

Internal Control Active, Continuous, Activat

Profile 0, Then 1, Then 2

110

Internal Control Active, Continuous, Activate

Profile 0, Then 1, Then 2, Then 3, Then Loop

Starting 0

111

Invalid

gle b

A sin

exec

urst mo

ich th

uted once. Fo

ume th

mp-up mod

FR1<29:2

Logic 010(b). Upon receiving an I/O U

ernal

ol logic sign

to begi

mode sequence fo

e 0. Upon rea

final address value for Profile 0, the de

ally

es to Profil

s execu

sequence. Upon r

M se

s value

rofile 1, the de

tically sw

ns executing

sequen

add

r Profile

er a

mposite sw

suing another I/O UPDATE restarts the burst process.

control mode is one in which the

de is one in wh

r example, ass

e composite sweep is

e device is programme

for ra

e and the C

7> bits are written to

PDATE, the int

contr

als the device

r Profil

n executing the ramp-up

ching the RAM segment

vice automatic

switch

e 1 and begin

eaching the RA

ting that ramp-up

gment final addres

for P

begi

vice automa

that ramp-up

lue fo

itches to Profile 2 and

ce. When the RAM

segment final

sequence is ov

ress va

nd the co

2 is reached, the

eep has completed.

A continuous internal profile

composite sweep is continuously executed for as long as the

device is programmed into that mode. Using the example

above, except programming the CFR1<29:27> bits to Logic

101(b), the operation would be identical until the RAM

segment final address value for Profile 2 is reached. At this

point, instead of stopping the sequence, it repeats, starting with

Profile 0.

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