5-9

25

CLOCK 1

Clock Input: External clock or ocsillator.

26

CLOCK 2

Clock Output: Crystal or RC oscillator.

27

MODE

INPUT LO: Direct output mode where CE/LD, HBEN, MBEN and LBEN act as inputs directly

controlling byte outputs. If pulsed HI causes immediate entry into handshake mode (see Figure

13). If HI, enables CE/LD, HBEN, MBEN and LBEN as outputs. Handshake mode will be entered

and data output as in Figures 11 and 12 at conversion completion.

28

R/H

pulses. Input LO conversion in progress completed, converter will stop in Auto-Zero 7 counts

before input integrate.

29

SEN

SEND ENABLE: Input controls timing of byte transmission in handshake mode. HI indicates

‘send’.

30

CE/LD

CHIP ENABLE/ LOAD: WITH MODE (PIN 27) LO, CE/LD serves as a master output enable;

when HI, the bit outputs and POL, OR are disabled. With MODE HI, pin serves as a LOAD strobe

(-ve going) used in handshake mode. See Figures 11 and 12.

31

V+

Positive Logic Supply Voltage: Nominally +5V.

32

AN I/P

Analog Input: High Side.

33

BUF IN

Buffer Input: Buffer Analog to analog chip (ICL8052 or ICL8086).

34

REFCAP2

Reference Capacitor: Negative Side.

35

AN. GND

Analog Ground: Input low side and reference low side.

36

A-Z

Auto-Zero node.

37

Voltage Reference: Input (positive side).

38

REFCAP1

Reference Capacitor: Positive side.

39

COMP-IN

Comparator Input: From 8052/8068.

40

V-

Negative Supply Voltage: Nominally -15V.

PIN NO.

SYMBOL

OPTION

DESCRIPTION

ICL8052/ICL7104, ICL8068/ICL7104