5-7

Pinouts

Functional Block Diagram

ICL8052/ICL8068

(CERDIP, PDIP)

TOP VIEW

ICL7104

(PDIP)

TOP VIEW

V-

COMP OUT

REF CAP

REF BYPASS

GND

REF OUT

REF SUPPLY

INT OUT

+BUFF IN

+INT IN

-INT IN

-BUFF IN

BUFF OUT

V++

1

2

3

4

5

6

7

14

13

12

11

10

9

8

-1.2V

ICL8052/

ICL8068

(OUTLINE DWGS DD, JD, PD)

13

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

17

18

19

20

V++

DIG GND

STTS

POL

OR

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

NC

NC

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

V-

COMP IN

REFCAP 1

AZ

ANALOG

REFCAP 2

BUF IN

ANALOG I/P

V+

CE/LD

SEN

R/H

MODE

CLK 2

CLK 1

CLK 3

HBEN

LBEN

BIT 1

ICL7104-14

GND

V++

DIG GND

STTS

POL

OR

BIT 16

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

ICL7104-14

ICL7104-16

ICL7104-14

ICL7104-16

HBEN

MBEN

(OUTLINE DWGS DL,

JL, PL)

FIGURE 1. ICL8052A (8068A)/ICL7104 16-BIT/14-BIT A/D CONVERTER FUNCTIONAL DIAGRAM

A2

+

-

A3

+

-

INTEG.

COMP.

A1

+

-

BUFFER

14

11

9

INT OUT

-INT IN

BUF OUT

10

-BUF IN

-1.2V

2

50k

Ω

-15V

+5V

1

-15V

7

8

+15V

12

+INT IN

13

8052/8068

INT.

REF.

6

3

+BUF IN

5

REF

OUT

5k

Ω

10k

Ω

300pF

10

µF

COMP

OUT

COMP IN

300k

Ω

39

36

33

8 9

6 7

12 13

10 11

16 17

14 15

20 21

18 19

5

4

14 13

16 15

10 9

12 11

6 5

87

2 1

43

OR POL

THREE-STATE OUTPUTS

LATCHES

COUNTER

24 HBEN

23 MBEN

22 LBEN

30 CE/LD

CONTROL LOGIC

ZERO

CROSSING

DETECTOR

29

27

28

7104

+BUF IN

AZ

SW3

SW5

SW4

SW6

SW8

SW2

SW9

SW7

SW1

34

REF CAP (2)

REF CAP (1)

38

37

32

35

ANALOG

GND

ANALOG

INPUT

SEN

MODE

R/H

BITS

3

STTS

26

CLOCK

25

CLOCK

40

-15V

2

1

+15V

31

+5V

(2)

(1)

ICL8052/ICL7104, ICL8068/ICL7104