AN4035 datasheet(9/42 Pages) STMICROELECTRONICS

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AN4035

JTAG

Doc ID 022669 Rev 2

9/41

the shifter to the register during the update-DR state. When reading a register, there is no

requirement to shift out the entire register contents. Shifting can be terminated after fetching

the required number of bits.

2.4.1

Reset

The JTAGC is placed in reset when the TAP controller state machine is in the TEST-LOGIC-

RESET state.

The TEST-LOGIC-RESET state is entered upon the assertion of the power-on reset signal,

negation of JCOMP, or through TAP controller state machine transitions controlled by TMS.

Asserting power-on reset or negating JCOMP results in asynchronous entry into the reset

state. While in reset, the following actions occur:

●

The TAP controller is forced into the test-logic-reset state, thereby disabling the test

logic and allowing normal operation of the on-chip system logic to continue unhindered.

●

The instruction register is loaded with the IDCODE instruction.

In addition, execution of EXTEST instruction results in assertion of the internal system reset.

2.4.2

Test mode

Several TEST modes are supported, as well as a bypass mode and they are entered using

the following instructions:

●

EXTEST

●

SAMPLE

●

SAMPLE/PRELOAD

Each instruction defines the set of data registers that can operate and interact with the on-

chip system logic while the instruction is current. Only one test data register path is enabled

to shift data between TDI and TDO for each instruction.

Following the test modes available:

BYPASS mode

When no test operation is required, the BYPASS instruction can be loaded to place the

JTAGC into bypass mode. While in bypass mode, the single-bit bypass shift register is

used to provide a minimum-length serial path to shift data between TDI and TDO.

TAP Sharing Mode

There are three selectable auxiliary TAP controllers that share the TAP with the

JTAGC. Selectable TAP controllers include:

- Nexus port controller (NPC)

- On Chip Emulator (ONCE) controller

- TCU controller

The instructions required to grant ownership of the TAP to the auxiliary TAP controllers are

ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_ONCE, ACCESS_AUX_TAP_TCU.

Instruction opcodes for each instruction are shown in Table 2.

When the access instruction for an auxiliary TAP is loaded, control of the JTAG pins is

transferred to the selected TAP controller. Any data input via TDI and TMS is passed to the

selected TAP controller, and any TDO output from the selected TAP controller is sent back

to the JTAGC to be output on the pins. The JTAGC regains control of the JTAG port during

the UPDATE-DR state if the PAUSE-DR state was entered. Auxiliary TAP controllers are

held in RUN-TEST/IDLE while they are inactive.

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